Mercurial > lcfOS
annotate python/cortexm3.py @ 276:56d37ed4b4d2
phaa
| author | Windel Bouwman |
|---|---|
| date | Mon, 16 Sep 2013 21:51:17 +0200 |
| parents | 6f2423df0675 |
| children | 046017431c6a |
| rev | line source |
|---|---|
| 261 | 1 import struct |
| 2 import types | |
| 275 | 3 from target import Register, Instruction, Target, Imm8, Label, Imm3, LabelRef, Imm32, Imm7 |
| 234 | 4 from asmnodes import ASymbol, ANumber, AUnop, ABinop |
| 202 | 5 from ppci import CompilerError |
| 205 | 6 import ir |
| 202 | 7 |
| 218 | 8 # TODO: encode this in DSL (domain specific language) |
| 275 | 9 # TBD: is this required? |
| 218 | 10 |
| 202 | 11 def u16(h): |
| 12 return struct.pack('<H', h) | |
| 13 | |
| 205 | 14 def u32(x): |
| 15 return struct.pack('<I', x) | |
| 16 | |
| 202 | 17 armtarget = Target('arm') |
| 18 | |
| 19 class ArmReg(Register): | |
| 20 def __init__(self, num, name): | |
| 21 super().__init__(name) | |
| 22 self.num = num | |
| 206 | 23 def __repr__(self): |
| 24 return self.name | |
| 202 | 25 |
| 203 | 26 class RegOp: |
| 27 def __init__(self, num): | |
| 206 | 28 assert num < 16 |
| 203 | 29 self.num = num |
| 30 | |
| 31 @classmethod | |
| 32 def Create(cls, vop): | |
| 33 if type(vop) is ASymbol: | |
| 34 name = vop.name | |
| 35 regs = {} | |
| 36 for r in armtarget.registers: | |
| 37 regs[r.name] = r | |
| 38 if name in regs: | |
| 39 r = regs[name] | |
| 40 return cls(r.num) | |
| 234 | 41 |
| 219 | 42 class Reg8Op: |
| 43 def __init__(self, num): | |
| 44 assert num < 8 | |
| 45 self.num = num | |
| 46 | |
| 47 @classmethod | |
| 48 def Create(cls, vop): | |
| 49 if type(vop) is ASymbol: | |
| 50 name = vop.name | |
| 51 regs = {} | |
| 52 for r in armtarget.registers: | |
| 53 regs[r.name] = r | |
| 54 if name in regs: | |
| 55 r = regs[name] | |
| 56 if r.num < 8: | |
| 57 return cls(r.num) | |
| 203 | 58 |
| 275 | 59 class Reg16Op: |
| 60 def __init__(self, num): | |
| 61 assert num < 16 | |
| 62 self.num = num | |
| 63 | |
| 64 @classmethod | |
| 65 def Create(cls, vop): | |
| 66 if type(vop) is ASymbol: | |
| 67 name = vop.name | |
| 68 regs = {} | |
| 69 for r in armtarget.registers: | |
| 70 regs[r.name] = r | |
| 71 if name in regs: | |
| 72 r = regs[name] | |
| 73 if r.num < 16: | |
| 74 return cls(r.num) | |
| 75 | |
| 76 class RegSpOp: | |
| 77 @classmethod | |
| 78 def Create(cls, vop): | |
| 79 if type(vop) is ASymbol: | |
| 80 if vop.name.lower() == 'sp': | |
| 81 return cls() | |
| 82 | |
| 206 | 83 def getRegNum(n): |
| 84 for r in armtarget.registers: | |
| 85 if r.num == n: | |
| 86 return r | |
| 203 | 87 |
| 206 | 88 def getRegisterRange(n1, n2): |
| 89 regs = [] | |
| 90 if n1.num < n2.num: | |
| 91 for n in range(n1.num, n2.num + 1): | |
| 92 r = getRegNum(n) | |
| 93 assert r | |
| 94 regs.append(r) | |
| 95 return regs | |
| 203 | 96 |
| 224 | 97 def isRegOffset(regname, x, y): |
| 98 if type(x) is ASymbol and type(y) is ANumber and x.name.upper() == regname: | |
| 99 return y.number | |
| 100 elif type(y) is ASymbol and type(x) is ANumber and y.name.upper() == regname: | |
| 101 return x.number | |
| 102 | |
| 103 | |
| 104 class MemRegXRel: | |
| 105 def __init__(self, offset): | |
| 106 assert offset % 4 == 0 | |
| 212 | 107 self.offset = offset |
| 108 | |
| 219 | 109 def __repr__(self): |
| 224 | 110 return '[{}, #{}]'.format(self.regname, self.offset) |
| 219 | 111 |
| 212 | 112 @classmethod |
| 113 def Create(cls, vop): | |
| 276 | 114 if type(vop) is AUnop and vop.operation == '[]' and type(vop.arg) is ABinop and vop.arg.op == '+': |
| 212 | 115 vop = vop.arg # descent |
| 224 | 116 offset = isRegOffset(cls.regname, vop.arg1, vop.arg2) |
| 117 if type(offset) is int: | |
| 118 if offset % 4 == 0: | |
| 223 | 119 offset = vop.arg2.number |
| 120 return cls(offset) | |
| 224 | 121 elif type(vop) is ASymbol and vop.name.upper() == self.regname: |
| 223 | 122 return cls(0) |
| 123 | |
| 276 | 124 |
| 224 | 125 class MemSpRel(MemRegXRel): |
| 126 regname = 'SP' | |
| 127 | |
| 128 | |
| 225 | 129 class MemR8Rel: |
| 219 | 130 def __init__(self, basereg, offset): |
| 131 assert type(basereg) is ArmReg | |
| 132 self.basereg = basereg | |
| 133 self.offset = offset | |
| 134 | |
| 135 def __repr__(self): | |
| 136 return '[{}, #{}]'.format(self.basereg, self.offset) | |
| 137 | |
| 138 @classmethod | |
| 139 def Create(cls, vop): | |
| 140 if type(vop) is AUnop and vop.operation == '[]': | |
| 141 vop = vop.arg # descent | |
| 142 if type(vop) is ABinop: | |
| 143 if vop.op == '+' and type(vop.arg1) is ASymbol and type(vop.arg2) is ANumber: | |
| 144 offset = vop.arg2.number | |
| 145 if offset > 120: | |
| 146 return | |
| 147 basereg = Reg8Op.Create(vop.arg1) | |
| 148 if not basereg: | |
| 149 return | |
| 150 else: | |
| 151 return | |
| 152 elif type(vop) is ASymbol: | |
| 153 offset = 0 | |
| 154 basereg = Reg8Op.Create(vop) | |
| 155 if not basereg: | |
| 156 return | |
| 157 else: | |
| 158 return | |
| 159 return cls(getRegNum(basereg.num), offset) | |
| 212 | 160 |
| 205 | 161 class RegisterSet: |
| 162 def __init__(self, regs): | |
| 206 | 163 assert type(regs) is set |
| 164 self.regs = regs | |
| 276 | 165 |
| 206 | 166 def __repr__(self): |
| 167 return ','.join([str(r) for r in self.regs]) | |
| 276 | 168 |
| 206 | 169 @classmethod |
| 170 def Create(cls, vop): | |
| 171 assert type(vop) is AUnop and vop.operation == '{}' | |
| 172 assert type(vop.arg) is list | |
| 173 regs = set() | |
| 174 for arg in vop.arg: | |
| 175 if type(arg) is ASymbol: | |
| 176 reg = RegOp.Create(arg) | |
| 177 if not reg: | |
| 178 return | |
| 179 regs.add(reg) | |
| 180 elif type(arg) is ABinop and arg.op == '-': | |
| 181 reg1 = RegOp.Create(arg.arg1) | |
| 182 reg2 = RegOp.Create(arg.arg2) | |
| 183 if not reg1: | |
| 184 return | |
| 185 if not reg2: | |
| 186 return | |
| 187 for r in getRegisterRange(reg1, reg2): | |
| 188 regs.add(r) | |
| 189 else: | |
| 190 raise Exception('Cannot be') | |
| 191 return cls(regs) | |
| 192 | |
| 193 def registerNumbers(self): | |
| 194 return [r.num for r in self.regs] | |
| 205 | 195 |
| 202 | 196 # 8 bit registers: |
| 205 | 197 r0 = ArmReg(0, 'r0') |
| 198 armtarget.registers.append(r0) | |
| 206 | 199 r1 = ArmReg(1, 'r1') |
| 200 armtarget.registers.append(r1) | |
| 201 r2 = ArmReg(2, 'r2') | |
| 202 armtarget.registers.append(r2) | |
| 203 r3 = ArmReg(3, 'r3') | |
| 204 armtarget.registers.append(r3) | |
| 202 | 205 r4 = ArmReg(4, 'r4') |
| 206 armtarget.registers.append(r4) | |
| 203 | 207 r5 = ArmReg(5, 'r5') |
| 208 armtarget.registers.append(r5) | |
| 209 r6 = ArmReg(6, 'r6') | |
| 210 armtarget.registers.append(r6) | |
| 211 r7 = ArmReg(7, 'r7') | |
| 212 armtarget.registers.append(r7) | |
| 206 | 213 # Other registers: |
| 214 # TODO | |
| 215 sp = ArmReg(13, 'sp') | |
| 216 armtarget.registers.append(sp) | |
| 217 lr = ArmReg(14, 'lr') | |
| 218 armtarget.registers.append(lr) | |
| 219 pc = ArmReg(15, 'pc') | |
| 220 armtarget.registers.append(pc) | |
| 202 | 221 |
| 276 | 222 |
| 202 | 223 class ArmInstruction(Instruction): |
| 224 pass | |
| 225 | |
| 235 | 226 |
| 227 @armtarget.instruction | |
| 205 | 228 class dcd_ins(ArmInstruction): |
| 229 mnemonic = 'dcd' | |
| 235 | 230 operands = (Imm32,) |
| 205 | 231 def __init__(self, expr): |
| 237 | 232 if isinstance(expr, Imm32): |
| 233 self.expr = expr.imm | |
| 234 self.label = None | |
| 235 elif isinstance(expr, LabelRef): | |
| 236 self.expr = 0 | |
| 237 self.label = expr | |
| 238 else: | |
| 239 raise NotImplementedError() | |
| 240 | |
| 241 def resolve(self, f): | |
| 242 if self.label: | |
| 243 self.expr = f(self.label.name) | |
| 219 | 244 |
| 205 | 245 def encode(self): |
| 246 return u32(self.expr) | |
| 202 | 247 |
| 219 | 248 def __repr__(self): |
| 249 return 'DCD 0x{0:X}'.format(self.expr) | |
| 250 | |
| 251 | |
| 252 | |
| 253 # Memory related | |
| 254 | |
| 255 class LS_imm5_base(ArmInstruction): | |
| 256 """ ??? Rt, [Rn, imm5] """ | |
| 225 | 257 operands = (Reg8Op, MemR8Rel) |
| 212 | 258 def __init__(self, rt, memop): |
| 259 assert memop.offset % 4 == 0 | |
| 260 self.imm5 = memop.offset >> 2 | |
| 261 self.rn = memop.basereg.num | |
| 225 | 262 self.rt = rt |
| 219 | 263 self.memloc = memop |
| 264 assert self.rn < 8 | |
| 225 | 265 assert self.rt.num < 8 |
| 212 | 266 |
| 267 def encode(self): | |
| 268 Rn = self.rn | |
| 225 | 269 Rt = self.rt.num |
| 212 | 270 imm5 = self.imm5 |
| 219 | 271 |
| 272 h = (self.opcode << 11) | (imm5 << 6) | (Rn << 3) | Rt | |
| 273 return u16(h) | |
| 275 | 274 |
| 219 | 275 def __repr__(self): |
| 276 return '{} {}, {}'.format(self.mnemonic, self.rt, self.memloc) | |
| 277 | |
| 278 @armtarget.instruction | |
| 279 class storeimm5_ins(LS_imm5_base): | |
| 280 mnemonic = 'STR' | |
| 281 opcode = 0xC | |
| 282 | |
| 283 @armtarget.instruction | |
| 284 class loadimm5_ins(LS_imm5_base): | |
| 285 mnemonic = 'LDR' | |
| 286 opcode = 0xD | |
| 287 | |
| 288 class ls_sp_base_imm8(ArmInstruction): | |
| 224 | 289 operands = (Reg8Op, MemSpRel) |
| 219 | 290 def __init__(self, rt, memop): |
| 291 self.rt = rt | |
| 292 self.offset = memop.offset | |
| 293 | |
| 294 def encode(self): | |
| 295 rt = self.rt.num | |
| 296 assert rt < 8 | |
| 297 imm8 = self.offset >> 2 | |
| 298 assert imm8 < 256 | |
| 299 h = (self.opcode << 8) | (rt << 8) | imm8 | |
| 212 | 300 return u16(h) |
| 301 | |
| 219 | 302 def __repr__(self): |
| 303 return '{} {}, [sp,#{}]'.format(self.mnemonic, self.rt, self.offset) | |
| 304 | |
| 236 | 305 def align(x, m): |
| 306 while ((x % m) != 0): | |
| 307 x = x + 1 | |
| 308 return x | |
| 309 | |
| 212 | 310 @armtarget.instruction |
| 219 | 311 class ldr_pcrel(ArmInstruction): |
| 276 | 312 """ ldr Rt, LABEL, load value from pc relative position """ |
| 212 | 313 mnemonic = 'ldr' |
| 235 | 314 operands = (RegOp, LabelRef) |
| 219 | 315 def __init__(self, rt, label): |
| 235 | 316 assert isinstance(label, LabelRef) |
| 219 | 317 self.rt = rt |
| 318 self.label = label | |
| 319 self.offset = 0 | |
| 212 | 320 |
| 234 | 321 def resolve(self, f): |
| 235 | 322 la = f(self.label.name) |
| 236 | 323 sa = align(self.address + 2, 4) |
| 324 self.offset = (la - sa) | |
| 235 | 325 if self.offset < 0: |
| 326 self.offset = 0 | |
| 234 | 327 |
| 212 | 328 def encode(self): |
| 219 | 329 rt = self.rt.num |
| 330 assert rt < 8 | |
| 331 imm8 = self.offset >> 2 | |
| 332 assert imm8 < 256 | |
| 235 | 333 assert imm8 >= 0 |
| 219 | 334 h = (0x9 << 11) | (rt << 8) | imm8 |
| 212 | 335 return u16(h) |
| 336 | |
| 219 | 337 def __repr__(self): |
| 232 | 338 return 'LDR {}, {}'.format(self.rt, self.label.name) |
| 219 | 339 |
| 340 @armtarget.instruction | |
| 341 class ldr_sprel(ls_sp_base_imm8): | |
| 342 """ ldr Rt, [SP, imm8] """ | |
| 343 mnemonic = 'LDR' | |
| 344 opcode = 0x98 | |
| 345 | |
| 346 @armtarget.instruction | |
| 347 class str_sprel(ls_sp_base_imm8): | |
| 348 """ str Rt, [SP, imm8] """ | |
| 349 mnemonic = 'STR' | |
| 350 opcode = 0x90 | |
| 351 | |
| 212 | 352 @armtarget.instruction |
| 202 | 353 class mov_ins(ArmInstruction): |
| 354 """ mov Rd, imm8, move immediate value into register """ | |
| 355 mnemonic = 'mov' | |
| 203 | 356 opcode = 4 # 00100 Rd(3) imm8 |
| 357 operands = (RegOp, Imm8) | |
| 358 def __init__(self, rd, imm): | |
| 359 self.imm = imm.imm | |
| 360 self.r = rd.num | |
| 205 | 361 |
| 202 | 362 def encode(self): |
| 363 rd = self.r | |
| 364 opcode = self.opcode | |
| 365 imm8 = self.imm | |
| 366 h = (opcode << 11) | (rd << 8) | imm8 | |
| 367 return u16(h) | |
| 219 | 368 def __repr__(self): |
| 369 return 'MOV {0}, xx?'.format(self.r) | |
| 232 | 370 |
| 371 | |
| 203 | 372 |
| 219 | 373 |
| 374 | |
| 375 # Arithmatics: | |
| 376 | |
| 275 | 377 |
| 378 | |
| 276 | 379 class regregimm3_base(ArmInstruction): |
| 380 operands = (Reg8Op, Reg8Op, Imm3) | |
| 203 | 381 def __init__(self, rd, rn, imm3): |
| 382 self.rd = rd | |
| 383 self.rn = rn | |
| 384 self.imm3 = imm3 | |
| 385 def encode(self): | |
| 386 rd = self.rd.num | |
| 387 rn = self.rn.num | |
| 388 imm3 = self.imm3.imm | |
| 389 opcode = self.opcode | |
| 276 | 390 h = (self.opcode << 9) | (imm3 << 6) | (rn << 3) | rd |
| 203 | 391 return u16(h) |
| 392 | |
| 276 | 393 |
| 394 @armtarget.instruction | |
| 395 class addregregimm3_ins(regregimm3_base): | |
| 396 """ add Rd, Rn, imm3 """ | |
| 397 mnemonic = 'add' | |
| 398 opcode = 0b0001110 | |
| 399 | |
| 400 | |
| 401 @armtarget.instruction | |
| 402 class subregregimm3_ins(regregimm3_base): | |
| 403 """ sub Rd, Rn, imm3 """ | |
| 404 mnemonic = 'sub' | |
| 405 opcode = 0b0001111 | |
| 406 | |
| 407 | |
| 219 | 408 class regregreg_base(ArmInstruction): |
| 409 """ ??? Rd, Rn, Rm """ | |
| 410 operands = (Reg8Op, Reg8Op, Reg8Op) | |
| 411 def __init__(self, rd, rn, rm): | |
| 412 self.rd = rd | |
| 413 self.rn = rn | |
| 414 self.rm = rm | |
| 415 def encode(self): | |
| 416 rd = self.rd.num | |
| 417 rn = self.rn.num | |
| 418 rm = self.rm.num | |
| 419 h = (self.opcode << 9) | (rm << 6) | (rn << 3) | rd | |
| 420 return u16(h) | |
| 421 def __repr__(self): | |
| 422 return '{} {}, {}, {}'.format(self.mnemonic, self.rd, self.rn, self.rm) | |
| 423 | |
| 424 @armtarget.instruction | |
| 425 class addregs_ins(regregreg_base): | |
| 426 mnemonic = 'ADD' | |
| 427 opcode = 0b0001100 | |
| 428 | |
| 429 @armtarget.instruction | |
| 430 class subregs_ins(regregreg_base): | |
| 431 mnemonic = 'SUB' | |
| 432 opcode = 0b0001101 | |
| 433 | |
| 275 | 434 |
| 435 @armtarget.instruction | |
| 436 class movregreg_ext_ins(ArmInstruction): | |
| 437 operands = (Reg16Op, Reg16Op) | |
| 438 mnemonic = 'MOV' | |
| 439 def __init__(self, rd, rm): | |
| 440 self.rd = rd | |
| 441 self.rm = rm | |
| 442 def encode(self): | |
| 443 Rd = self.rd.num & 0x7 | |
| 444 D = (self.rd.num >> 3) & 0x1 | |
| 445 Rm = self.rm.num | |
| 446 opcode = 0b01000110 | |
| 447 return u16((opcode << 8) | (D << 7) |(Rm << 3) | Rd) | |
| 448 def __repr__(self): | |
| 449 return '{} {}, {}'.format(self.mnemonic, self.rd, self.rm) | |
| 450 | |
| 451 | |
| 276 | 452 @armtarget.instruction |
| 453 class mulregreg_ins(ArmInstruction): | |
| 454 """ mul Rn, Rdm """ | |
| 455 operands = (Reg8Op, Reg8Op) | |
| 456 mnemonic = 'mul' | |
| 457 def __init__(self, rn, rdm): | |
| 458 self.rn = rn | |
| 459 self.rdm = rdm | |
| 460 def encode(self): | |
| 461 rn = self.rn.num | |
| 462 rdm = self.rdm.num | |
| 463 opcode = 0b0100001101 | |
| 464 h = (opcode << 6) | (rn << 3) | rdm | |
| 465 return u16(h) | |
| 466 def __repr__(self): | |
| 467 return '{} {}, {}'.format(self.mnemonic, self.rdn, self.rm) | |
| 275 | 468 |
| 219 | 469 class regreg_base(ArmInstruction): |
| 470 """ ??? Rdn, Rm """ | |
| 471 operands = (Reg8Op, Reg8Op) | |
| 472 def __init__(self, rdn, rm): | |
| 473 self.rdn = rdn | |
| 474 self.rm = rm | |
| 475 def encode(self): | |
| 476 rdn = self.rdn.num | |
| 477 rm = self.rm.num | |
| 478 h = (self.opcode << 6) | (rm << 3) | rdn | |
| 479 return u16(h) | |
| 480 def __repr__(self): | |
| 481 return '{} {}, {}'.format(self.mnemonic, self.rdn, self.rm) | |
| 482 | |
| 483 @armtarget.instruction | |
| 258 | 484 class movregreg_ins(regreg_base): |
| 485 """ mov Rd, Rm """ | |
| 486 mnemonic = 'mov' | |
| 487 opcode = 0 | |
| 488 | |
| 489 @armtarget.instruction | |
| 219 | 490 class andregs_ins(regreg_base): |
| 491 mnemonic = 'AND' | |
| 492 opcode = 0b0100000000 | |
| 493 | |
| 494 @armtarget.instruction | |
| 495 class orrregs_ins(regreg_base): | |
| 496 mnemonic = 'ORR' | |
| 497 opcode = 0b0100001100 | |
| 498 | |
| 499 @armtarget.instruction | |
| 500 class cmp_ins(regreg_base): | |
| 501 mnemonic = 'CMP' | |
| 502 opcode = 0b0100001010 | |
| 503 | |
| 203 | 504 @armtarget.instruction |
| 232 | 505 class lslregs_ins(regreg_base): |
| 506 mnemonic = 'LSL' | |
| 507 opcode = 0b0100000010 | |
| 508 | |
| 509 @armtarget.instruction | |
| 203 | 510 class cmpregimm8_ins(ArmInstruction): |
| 511 """ cmp Rn, imm8 """ | |
| 512 mnemonic = 'cmp' | |
| 513 opcode = 5 # 00101 | |
| 514 operands = (RegOp, Imm8) | |
| 515 def __init__(self, rn, imm): | |
| 516 self.rn = rn | |
| 517 self.imm = imm | |
| 518 def encode(self): | |
| 519 rn = self.rn.num | |
| 520 imm = self.imm.imm | |
| 521 opcode = self.opcode | |
| 522 h = (opcode << 11) | (rn << 8) | imm | |
| 523 return u16(h) | |
| 202 | 524 |
| 219 | 525 # Jumping: |
| 218 | 526 |
| 238 | 527 def wrap_negative(x, bits): |
| 528 b = struct.unpack('<I', struct.pack('<i', x))[0] | |
| 529 mask = (1 << bits) - 1 | |
| 530 return b & mask | |
| 531 | |
| 237 | 532 class jumpBase_ins(ArmInstruction): |
| 533 operands = (LabelRef,) | |
| 205 | 534 def __init__(self, target_label): |
| 237 | 535 assert type(target_label) is LabelRef |
| 205 | 536 self.target = target_label |
| 237 | 537 self.offset = 0 |
| 538 | |
| 539 def resolve(self, f): | |
| 540 la = f(self.target.name) | |
| 238 | 541 sa = self.address + 4 |
| 237 | 542 self.offset = (la - sa) |
| 238 | 543 #if self.offset < 0: |
| 544 # # TODO: handle negative jump | |
| 545 # self.offset = 0 | |
| 237 | 546 |
| 219 | 547 def __repr__(self): |
| 237 | 548 return '{} {}'.format(self.mnemonic, self.target.name) |
| 219 | 549 |
| 550 @armtarget.instruction | |
| 237 | 551 class b_ins(jumpBase_ins): |
| 552 mnemonic = 'B' | |
| 553 def encode(self): | |
| 238 | 554 imm11 = wrap_negative(self.offset >> 1, 11) |
| 555 h = (0b11100 << 11) | imm11 # | 1 # 1 to enable thumb mode | |
| 237 | 556 return u16(h) |
| 557 | |
|
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558 @armtarget.instruction |
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559 class bl_ins(jumpBase_ins): |
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560 mnemonic = 'BL' |
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561 def encode(self): |
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562 imm32 = wrap_negative(self.offset >> 1, 32) |
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563 imm11 = imm32 & 0x7FF |
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564 imm10 = (imm32 >> 11) & 0x3FF |
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565 j1 = 1 # TODO: what do these mean? |
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566 j2 = 1 |
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567 s = (imm32 >> 24) & 0x1 |
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568 h1 = (0b11110 << 11) | (s << 10) | imm10 |
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569 h2 = (0b1101 << 12) | (j1 << 13) | (j2 << 11) | imm11 |
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570 return u16(h1) + u16(h2) |
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571 |
| 237 | 572 class cond_base_ins(jumpBase_ins): |
| 573 def encode(self): | |
| 238 | 574 imm8 = wrap_negative(self.offset >> 1, 8) |
| 237 | 575 h = (0b1101 << 12) | (self.cond << 8) | imm8 |
| 576 return u16(h) | |
| 577 | |
| 262 | 578 |
| 237 | 579 @armtarget.instruction |
| 580 class beq_ins(cond_base_ins): | |
| 219 | 581 mnemonic = 'beq' |
| 237 | 582 cond = 0 |
| 583 | |
| 262 | 584 |
| 237 | 585 @armtarget.instruction |
| 262 | 586 class bne_ins(cond_base_ins): |
| 237 | 587 mnemonic = 'bne' |
| 588 cond = 1 | |
| 205 | 589 |
| 262 | 590 |
| 591 @armtarget.instruction | |
| 592 class blt_ins(cond_base_ins): | |
| 593 mnemonic = 'blt' | |
| 594 cond = 0b1011 | |
| 595 | |
| 596 | |
| 597 @armtarget.instruction | |
| 598 class blt_ins(cond_base_ins): | |
| 599 mnemonic = 'bgt' | |
| 600 cond = 0b1100 | |
| 601 | |
| 602 | |
| 205 | 603 @armtarget.instruction |
| 604 class push_ins(ArmInstruction): | |
| 206 | 605 operands = (RegisterSet,) |
| 205 | 606 mnemonic = 'push' |
| 607 def __init__(self, regs): | |
| 206 | 608 assert (type(regs),) == self.operands, (type(regs),) |
| 205 | 609 self.regs = regs |
| 206 | 610 def __repr__(self): |
| 611 return '{0} {{{1}}}'.format(self.mnemonic, self.regs) | |
| 205 | 612 def encode(self): |
| 206 | 613 reg_list = 0 |
| 614 M = 0 | |
| 615 for n in self.regs.registerNumbers(): | |
| 616 if n < 8: | |
| 617 reg_list |= (1 << n) | |
| 618 elif n == 14: | |
| 619 M = 1 | |
| 620 else: | |
| 621 raise NotImplementedError('not implemented for this register') | |
| 622 h = (0x5a << 9) | (M << 8) | reg_list | |
| 623 return u16(h) | |
| 205 | 624 |
| 625 @armtarget.instruction | |
| 626 class pop_ins(ArmInstruction): | |
| 206 | 627 operands = (RegisterSet,) |
| 205 | 628 mnemonic = 'pop' |
| 629 def __init__(self, regs): | |
| 630 self.regs = regs | |
| 207 | 631 def __repr__(self): |
| 632 return '{0} {{{1}}}'.format(self.mnemonic, self.regs) | |
| 205 | 633 def encode(self): |
| 206 | 634 reg_list = 0 |
| 635 P = 0 | |
| 636 for n in self.regs.registerNumbers(): | |
| 637 if n < 8: | |
| 638 reg_list |= (1 << n) | |
| 639 elif n == 15: | |
| 640 P = 1 | |
| 641 else: | |
| 642 raise NotImplementedError('not implemented for this register') | |
| 643 h = (0x5E << 9) | (P << 8) | reg_list | |
| 644 return u16(h) | |
| 205 | 645 |
| 646 @armtarget.instruction | |
| 202 | 647 class yield_ins(ArmInstruction): |
| 648 operands = () | |
| 649 mnemonic = 'yield' | |
| 650 def encode(self): | |
| 651 return u16(0xbf10) | |
| 652 | |
| 275 | 653 # misc: |
| 654 | |
| 655 # add/sub SP: | |
| 656 @armtarget.instruction | |
| 657 class addspsp_ins(ArmInstruction): | |
| 658 operands = (RegSpOp, RegSpOp, Imm7) | |
| 659 mnemonic = 'add' | |
| 660 def __init__(self, _sp, _sp2, imm7): | |
| 661 self.imm7 = imm7.imm | |
| 662 assert self.imm7 % 4 == 0 | |
| 663 self.imm7 >>= 2 | |
| 664 | |
| 665 def encode(self): | |
| 666 return u16((0b101100000 << 7) |self.imm7) | |
| 667 | |
| 668 @armtarget.instruction | |
| 669 class subspsp_ins(ArmInstruction): | |
| 670 operands = (RegSpOp, RegSpOp, Imm7) | |
| 671 mnemonic = 'sub' | |
| 672 def __init__(self, _sp, _sp2, imm7): | |
| 673 self.imm7 = imm7.imm | |
| 674 assert self.imm7 % 4 == 0 | |
| 675 self.imm7 >>= 2 | |
| 676 | |
| 677 def encode(self): | |
| 678 return u16((0b101100001 << 7) |self.imm7) | |
| 679 | |
| 206 | 680 armtarget.check() |
| 681 |