--- a/python/arm_cm3.py	Sat Jun 29 10:10:45 2013 +0200
+++ b/python/arm_cm3.py	Sun Jun 30 19:00:41 2013 +0200
@@ -49,6 +49,34 @@
             regs.append(r)
     return regs
 
+class MemoryOp:
+    def __init__(self, basereg, offset):
+        assert type(basereg) is ArmReg
+        self.basereg = basereg
+        self.offset = offset
+
+    @classmethod
+    def Create(cls, vop):
+        if type(vop) is AUnop and vop.operation == '[]':
+            vop = vop.arg # descent
+            if type(vop) is ABinop:
+                if vop.op == '+' and type(vop.arg1) is ASymbol and type(vop.arg2) is ANumber:
+                    offset = vop.arg2.number
+                    basereg = RegOp.Create(vop.arg1)
+                    if not basereg:
+                        return
+                else:
+                    return
+            elif type(vop) is ASymbol:
+                offset = 0
+                basereg = RegOp.Create(vop)
+                if not basereg:
+                    return
+            else:
+                return
+            return cls(getRegNum(basereg.num), offset)
+        pass
+
 class RegisterSet:
     def __init__(self, regs):
         assert type(regs) is set
@@ -124,6 +152,42 @@
         return u32(self.expr)
 
 @armtarget.instruction
+class storeimm5_ins(ArmInstruction):
+    """ str Rt, [Rn, imm5], store value into memory """
+    mnemonic = 'str'
+    operands = (RegOp, MemoryOp)
+    def __init__(self, rt, memop):
+        assert memop.offset % 4 == 0
+        self.imm5 = memop.offset >> 2
+        self.rn = memop.basereg.num
+        self.rt = rt.num
+
+    def encode(self):
+        Rn = self.rn
+        Rt = self.rt
+        imm5 = self.imm5
+        h = (0xC << 11) | (imm5 << 6) | (Rn << 3) | Rt
+        return u16(h)
+
+@armtarget.instruction
+class loadimm5_ins(ArmInstruction):
+    """ str Rt, [Rn, imm5], store value into memory """
+    mnemonic = 'ldr'
+    operands = (RegOp, MemoryOp)
+    def __init__(self, rt, memop):
+        assert memop.offset % 4 == 0
+        self.imm5 = memop.offset >> 2
+        self.rn = memop.basereg.num
+        self.rt = rt.num
+
+    def encode(self):
+        Rn = self.rn
+        Rt = self.rt
+        imm5 = self.imm5
+        h = (0xD << 11) | (imm5 << 6) | (Rn << 3) | Rt
+        return u16(h)
+
+@armtarget.instruction
 class mov_ins(ArmInstruction):
     """ mov Rd, imm8, move immediate value into register """
     mnemonic = 'mov'