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comparison python/cortexm3.py @ 276:56d37ed4b4d2

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phaa
author Windel Bouwman
date Mon, 16 Sep 2013 21:51:17 +0200
parents 6f2423df0675
children 046017431c6a
comparison
equal deleted inserted replaced
275:6f2423df0675 276:56d37ed4b4d2
109 def __repr__(self): 109 def __repr__(self):
110 return '[{}, #{}]'.format(self.regname, self.offset) 110 return '[{}, #{}]'.format(self.regname, self.offset)
111 111
112 @classmethod 112 @classmethod
113 def Create(cls, vop): 113 def Create(cls, vop):
114 if type(vop) is AUnop and vop.operation == '[]': 114 if type(vop) is AUnop and vop.operation == '[]' and type(vop.arg) is ABinop and vop.arg.op == '+':
115 vop = vop.arg # descent 115 vop = vop.arg # descent
116 offset = isRegOffset(cls.regname, vop.arg1, vop.arg2) 116 offset = isRegOffset(cls.regname, vop.arg1, vop.arg2)
117 if type(offset) is int: 117 if type(offset) is int:
118 if offset % 4 == 0: 118 if offset % 4 == 0:
119 offset = vop.arg2.number 119 offset = vop.arg2.number
120 return cls(offset) 120 return cls(offset)
121 elif type(vop) is ASymbol and vop.name.upper() == self.regname: 121 elif type(vop) is ASymbol and vop.name.upper() == self.regname:
122 return cls(0) 122 return cls(0)
123 123
124
124 class MemSpRel(MemRegXRel): 125 class MemSpRel(MemRegXRel):
125 regname = 'SP' 126 regname = 'SP'
126 127
127 class MemPcRel(MemRegXRel):
128 regname = 'PC'
129 128
130 class MemR8Rel: 129 class MemR8Rel:
131 def __init__(self, basereg, offset): 130 def __init__(self, basereg, offset):
132 assert type(basereg) is ArmReg 131 assert type(basereg) is ArmReg
133 self.basereg = basereg 132 self.basereg = basereg
161 160
162 class RegisterSet: 161 class RegisterSet:
163 def __init__(self, regs): 162 def __init__(self, regs):
164 assert type(regs) is set 163 assert type(regs) is set
165 self.regs = regs 164 self.regs = regs
165
166 def __repr__(self): 166 def __repr__(self):
167 return ','.join([str(r) for r in self.regs]) 167 return ','.join([str(r) for r in self.regs])
168
168 @classmethod 169 @classmethod
169 def Create(cls, vop): 170 def Create(cls, vop):
170 assert type(vop) is AUnop and vop.operation == '{}' 171 assert type(vop) is AUnop and vop.operation == '{}'
171 assert type(vop.arg) is list 172 assert type(vop.arg) is list
172 regs = set() 173 regs = set()
216 lr = ArmReg(14, 'lr') 217 lr = ArmReg(14, 'lr')
217 armtarget.registers.append(lr) 218 armtarget.registers.append(lr)
218 pc = ArmReg(15, 'pc') 219 pc = ArmReg(15, 'pc')
219 armtarget.registers.append(pc) 220 armtarget.registers.append(pc)
220 221
222
221 class ArmInstruction(Instruction): 223 class ArmInstruction(Instruction):
222 pass 224 pass
223 225
224 226
225 @armtarget.instruction 227 @armtarget.instruction
305 x = x + 1 307 x = x + 1
306 return x 308 return x
307 309
308 @armtarget.instruction 310 @armtarget.instruction
309 class ldr_pcrel(ArmInstruction): 311 class ldr_pcrel(ArmInstruction):
310 """ ldr Rt, [PC, imm8], store value into memory """ 312 """ ldr Rt, LABEL, load value from pc relative position """
311 mnemonic = 'ldr' 313 mnemonic = 'ldr'
312 operands = (RegOp, LabelRef) 314 operands = (RegOp, LabelRef)
313 def __init__(self, rt, label): 315 def __init__(self, rt, label):
314 assert isinstance(label, LabelRef) 316 assert isinstance(label, LabelRef)
315 self.rt = rt 317 self.rt = rt
372 374
373 # Arithmatics: 375 # Arithmatics:
374 376
375 377
376 378
377 @armtarget.instruction 379 class regregimm3_base(ArmInstruction):
378 class addregregimm3_ins(ArmInstruction): 380 operands = (Reg8Op, Reg8Op, Imm3)
379 """ add Rd, Rn, imm3 """
380 mnemonic = 'add'
381 opcode = 3 # 00011
382 operands = (RegOp, RegOp, Imm3)
383 irpattern = 3
384 def __init__(self, rd, rn, imm3): 381 def __init__(self, rd, rn, imm3):
385 self.rd = rd 382 self.rd = rd
386 self.rn = rn 383 self.rn = rn
387 self.imm3 = imm3 384 self.imm3 = imm3
388 def encode(self): 385 def encode(self):
389 rd = self.rd.num 386 rd = self.rd.num
390 rn = self.rn.num 387 rn = self.rn.num
391 imm3 = self.imm3.imm 388 imm3 = self.imm3.imm
392 opcode = self.opcode 389 opcode = self.opcode
393 h = (opcode << 11) | (1 << 10) | (imm3 << 6) | (rn << 3) | rd 390 h = (self.opcode << 9) | (imm3 << 6) | (rn << 3) | rd
394 return u16(h) 391 return u16(h)
392
393
394 @armtarget.instruction
395 class addregregimm3_ins(regregimm3_base):
396 """ add Rd, Rn, imm3 """
397 mnemonic = 'add'
398 opcode = 0b0001110
399
400
401 @armtarget.instruction
402 class subregregimm3_ins(regregimm3_base):
403 """ sub Rd, Rn, imm3 """
404 mnemonic = 'sub'
405 opcode = 0b0001111
406
395 407
396 class regregreg_base(ArmInstruction): 408 class regregreg_base(ArmInstruction):
397 """ ??? Rd, Rn, Rm """ 409 """ ??? Rd, Rn, Rm """
398 operands = (Reg8Op, Reg8Op, Reg8Op) 410 operands = (Reg8Op, Reg8Op, Reg8Op)
399 def __init__(self, rd, rn, rm): 411 def __init__(self, rd, rn, rm):
435 return u16((opcode << 8) | (D << 7) |(Rm << 3) | Rd) 447 return u16((opcode << 8) | (D << 7) |(Rm << 3) | Rd)
436 def __repr__(self): 448 def __repr__(self):
437 return '{} {}, {}'.format(self.mnemonic, self.rd, self.rm) 449 return '{} {}, {}'.format(self.mnemonic, self.rd, self.rm)
438 450
439 451
452 @armtarget.instruction
453 class mulregreg_ins(ArmInstruction):
454 """ mul Rn, Rdm """
455 operands = (Reg8Op, Reg8Op)
456 mnemonic = 'mul'
457 def __init__(self, rn, rdm):
458 self.rn = rn
459 self.rdm = rdm
460 def encode(self):
461 rn = self.rn.num
462 rdm = self.rdm.num
463 opcode = 0b0100001101
464 h = (opcode << 6) | (rn << 3) | rdm
465 return u16(h)
466 def __repr__(self):
467 return '{} {}, {}'.format(self.mnemonic, self.rdn, self.rm)
440 468
441 class regreg_base(ArmInstruction): 469 class regreg_base(ArmInstruction):
442 """ ??? Rdn, Rm """ 470 """ ??? Rdn, Rm """
443 operands = (Reg8Op, Reg8Op) 471 operands = (Reg8Op, Reg8Op)
444 def __init__(self, rdn, rm): 472 def __init__(self, rdn, rm):