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205
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1 import struct, types
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206
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2 from target import Register, Instruction, Target, Imm8, Label, Imm3
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219
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3 from asmnodes import ASymbol, ANumber, AUnop, ABinop, ALabel
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202
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4 from ppci import CompilerError
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205
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5 import ir
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202
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6
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218
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7 # TODO: encode this in DSL (domain specific language)
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8
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202
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9 def u16(h):
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10 return struct.pack('<H', h)
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11
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205
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12 def u32(x):
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13 return struct.pack('<I', x)
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14
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202
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15 armtarget = Target('arm')
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16
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17 class ArmReg(Register):
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18 def __init__(self, num, name):
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19 super().__init__(name)
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20 self.num = num
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206
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21 def __repr__(self):
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22 return self.name
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202
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23
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203
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24 class RegOp:
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25 def __init__(self, num):
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206
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26 assert num < 16
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203
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27 self.num = num
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28
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29 @classmethod
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30 def Create(cls, vop):
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31 if type(vop) is ASymbol:
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32 name = vop.name
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33 regs = {}
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34 for r in armtarget.registers:
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35 regs[r.name] = r
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36 if name in regs:
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37 r = regs[name]
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38 return cls(r.num)
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219
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39
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40 class Reg8Op:
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41 def __init__(self, num):
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42 assert num < 8
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43 self.num = num
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44
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45 @classmethod
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46 def Create(cls, vop):
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47 if type(vop) is ASymbol:
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48 name = vop.name
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49 regs = {}
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50 for r in armtarget.registers:
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51 regs[r.name] = r
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52 if name in regs:
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53 r = regs[name]
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54 if r.num < 8:
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55 return cls(r.num)
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203
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56
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206
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57 def getRegNum(n):
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58 for r in armtarget.registers:
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59 if r.num == n:
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60 return r
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203
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61
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206
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62 def getRegisterRange(n1, n2):
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63 regs = []
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64 if n1.num < n2.num:
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65 for n in range(n1.num, n2.num + 1):
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66 r = getRegNum(n)
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67 assert r
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68 regs.append(r)
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69 return regs
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203
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70
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224
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71 def isRegOffset(regname, x, y):
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72 if type(x) is ASymbol and type(y) is ANumber and x.name.upper() == regname:
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73 return y.number
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74 elif type(y) is ASymbol and type(x) is ANumber and y.name.upper() == regname:
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75 return x.number
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76
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77
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78 class MemRegXRel:
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79 def __init__(self, offset):
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80 assert offset % 4 == 0
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212
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81 self.offset = offset
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82
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219
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83 def __repr__(self):
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224
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84 return '[{}, #{}]'.format(self.regname, self.offset)
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219
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85
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212
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86 @classmethod
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87 def Create(cls, vop):
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88 if type(vop) is AUnop and vop.operation == '[]':
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89 vop = vop.arg # descent
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224
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90 offset = isRegOffset(cls.regname, vop.arg1, vop.arg2)
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91 if type(offset) is int:
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92 if offset % 4 == 0:
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223
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93 offset = vop.arg2.number
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94 return cls(offset)
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224
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95 elif type(vop) is ASymbol and vop.name.upper() == self.regname:
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223
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96 return cls(0)
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97
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224
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98 class MemSpRel(MemRegXRel):
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99 regname = 'SP'
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100
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101 class MemPcRel(MemRegXRel):
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102 regname = 'PC'
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103
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225
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104 class MemR8Rel:
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219
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105 def __init__(self, basereg, offset):
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106 assert type(basereg) is ArmReg
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107 self.basereg = basereg
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108 self.offset = offset
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109
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110 def __repr__(self):
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111 return '[{}, #{}]'.format(self.basereg, self.offset)
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112
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113 @classmethod
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114 def Create(cls, vop):
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115 if type(vop) is AUnop and vop.operation == '[]':
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116 vop = vop.arg # descent
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117 if type(vop) is ABinop:
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118 if vop.op == '+' and type(vop.arg1) is ASymbol and type(vop.arg2) is ANumber:
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119 offset = vop.arg2.number
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120 if offset > 120:
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121 return
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122 basereg = Reg8Op.Create(vop.arg1)
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123 if not basereg:
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124 return
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125 else:
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126 return
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127 elif type(vop) is ASymbol:
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128 offset = 0
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129 basereg = Reg8Op.Create(vop)
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130 if not basereg:
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131 return
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132 else:
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133 return
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134 return cls(getRegNum(basereg.num), offset)
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212
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135
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205
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136 class RegisterSet:
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137 def __init__(self, regs):
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206
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138 assert type(regs) is set
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139 self.regs = regs
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140 def __repr__(self):
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141 return ','.join([str(r) for r in self.regs])
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142 @classmethod
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143 def Create(cls, vop):
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144 assert type(vop) is AUnop and vop.operation == '{}'
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145 assert type(vop.arg) is list
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146 regs = set()
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147 for arg in vop.arg:
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148 if type(arg) is ASymbol:
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149 reg = RegOp.Create(arg)
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150 if not reg:
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151 return
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152 regs.add(reg)
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153 elif type(arg) is ABinop and arg.op == '-':
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154 reg1 = RegOp.Create(arg.arg1)
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155 reg2 = RegOp.Create(arg.arg2)
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156 if not reg1:
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157 return
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158 if not reg2:
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159 return
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160 for r in getRegisterRange(reg1, reg2):
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161 regs.add(r)
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162 else:
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163 raise Exception('Cannot be')
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164 return cls(regs)
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165
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166 def registerNumbers(self):
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167 return [r.num for r in self.regs]
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205
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168
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202
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169 # 8 bit registers:
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170 r0 = ArmReg(0, 'r0')
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171 armtarget.registers.append(r0)
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206
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172 r1 = ArmReg(1, 'r1')
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173 armtarget.registers.append(r1)
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174 r2 = ArmReg(2, 'r2')
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175 armtarget.registers.append(r2)
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176 r3 = ArmReg(3, 'r3')
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177 armtarget.registers.append(r3)
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202
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178 r4 = ArmReg(4, 'r4')
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179 armtarget.registers.append(r4)
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203
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180 r5 = ArmReg(5, 'r5')
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181 armtarget.registers.append(r5)
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182 r6 = ArmReg(6, 'r6')
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183 armtarget.registers.append(r6)
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184 r7 = ArmReg(7, 'r7')
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185 armtarget.registers.append(r7)
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206
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186 # Other registers:
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187 # TODO
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188 sp = ArmReg(13, 'sp')
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189 armtarget.registers.append(sp)
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190 lr = ArmReg(14, 'lr')
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191 armtarget.registers.append(lr)
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192 pc = ArmReg(15, 'pc')
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193 armtarget.registers.append(pc)
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202
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194
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195 class ArmInstruction(Instruction):
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196 pass
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197
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205
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198 class dcd_ins(ArmInstruction):
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199 mnemonic = 'dcd'
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200 def __init__(self, expr):
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201 self.expr = expr
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219
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202
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205
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203 def encode(self):
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204 return u32(self.expr)
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202
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205
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219
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206 def __repr__(self):
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207 return 'DCD 0x{0:X}'.format(self.expr)
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208
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209
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210
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211 # Memory related
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212
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213 class LS_imm5_base(ArmInstruction):
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214 """ ??? Rt, [Rn, imm5] """
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225
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215 operands = (Reg8Op, MemR8Rel)
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212
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216 def __init__(self, rt, memop):
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217 assert memop.offset % 4 == 0
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218 self.imm5 = memop.offset >> 2
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219 self.rn = memop.basereg.num
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225
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220 self.rt = rt
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219
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221 self.memloc = memop
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222 assert self.rn < 8
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225
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223 assert self.rt.num < 8
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212
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224
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225 def encode(self):
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226 Rn = self.rn
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225
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227 Rt = self.rt.num
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212
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228 imm5 = self.imm5
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219
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229
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230 h = (self.opcode << 11) | (imm5 << 6) | (Rn << 3) | Rt
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231 return u16(h)
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232 def __repr__(self):
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233 return '{} {}, {}'.format(self.mnemonic, self.rt, self.memloc)
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234
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235 @armtarget.instruction
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236 class storeimm5_ins(LS_imm5_base):
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237 mnemonic = 'STR'
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238 opcode = 0xC
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239
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240 @armtarget.instruction
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241 class loadimm5_ins(LS_imm5_base):
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242 mnemonic = 'LDR'
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243 opcode = 0xD
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244
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245 class ls_sp_base_imm8(ArmInstruction):
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224
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246 operands = (Reg8Op, MemSpRel)
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219
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247 def __init__(self, rt, memop):
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248 self.rt = rt
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249 self.offset = memop.offset
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250
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251 def encode(self):
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252 rt = self.rt.num
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253 assert rt < 8
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254 imm8 = self.offset >> 2
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255 assert imm8 < 256
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256 h = (self.opcode << 8) | (rt << 8) | imm8
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212
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257 return u16(h)
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258
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219
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259 def __repr__(self):
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260 return '{} {}, [sp,#{}]'.format(self.mnemonic, self.rt, self.offset)
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261
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212
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262 @armtarget.instruction
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219
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263 class ldr_pcrel(ArmInstruction):
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264 """ ldr Rt, [PC, imm8], store value into memory """
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212
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265 mnemonic = 'ldr'
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224
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266 operands = (RegOp, MemPcRel)
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219
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267 def __init__(self, rt, label):
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268 self.rt = rt
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269 self.label = label
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270 self.offset = 0
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212
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271
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272 def encode(self):
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219
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273 rt = self.rt.num
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274 assert rt < 8
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275 imm8 = self.offset >> 2
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276 assert imm8 < 256
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277 h = (0x9 << 11) | (rt << 8) | imm8
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212
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278 return u16(h)
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279
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219
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280 def __repr__(self):
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281 return 'LDR {}, [pc,#{}]'.format(self.rt, self.offset)
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282
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283 @armtarget.instruction
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284 class ldr_sprel(ls_sp_base_imm8):
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285 """ ldr Rt, [SP, imm8] """
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286 mnemonic = 'LDR'
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287 opcode = 0x98
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288
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289 @armtarget.instruction
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290 class str_sprel(ls_sp_base_imm8):
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291 """ str Rt, [SP, imm8] """
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292 mnemonic = 'STR'
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293 opcode = 0x90
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294
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212
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295 @armtarget.instruction
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202
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296 class mov_ins(ArmInstruction):
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297 """ mov Rd, imm8, move immediate value into register """
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298 mnemonic = 'mov'
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203
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299 opcode = 4 # 00100 Rd(3) imm8
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300 operands = (RegOp, Imm8)
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205
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301 irpattern = ir.ImmLoad
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203
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302 def __init__(self, rd, imm):
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303 self.imm = imm.imm
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304 self.r = rd.num
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205
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305
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202
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306 def encode(self):
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307 rd = self.r
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308 opcode = self.opcode
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309 imm8 = self.imm
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310 h = (opcode << 11) | (rd << 8) | imm8
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311 return u16(h)
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219
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312 def __repr__(self):
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313 return 'MOV {0}, xx?'.format(self.r)
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202
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314
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203
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315 @armtarget.instruction
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316 class movregreg_ins(ArmInstruction):
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317 """ mov Rd, Rm """
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318 mnemonic = 'mov'
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319 operands = (RegOp, RegOp)
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320 def __init__(self, rd, rm):
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321 self.rd = rd
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322 self.rm = rm
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323 def encode(self):
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324 rd = self.rd.num
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325 D = (rd & 0x8) >> 3
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326 assert D < 2
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327 rd = rd & 0x7
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328 rm = self.rm.num
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329 assert rm < 16
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330 opcode = self.opcode
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219
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331 h = (1 << 14) | (3 << 9) | (D << 7) | (rm << 3) | rd
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203
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332 return u16(h)
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333
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219
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334
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335
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336 # Arithmatics:
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337
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203
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338 @armtarget.instruction
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339 class addregregimm3_ins(ArmInstruction):
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340 """ add Rd, Rn, imm3 """
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341 mnemonic = 'add'
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342 opcode = 3 # 00011
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343 operands = (RegOp, RegOp, Imm3)
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205
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344 irpattern = 3
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203
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345 def __init__(self, rd, rn, imm3):
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346 self.rd = rd
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347 self.rn = rn
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348 self.imm3 = imm3
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349 def encode(self):
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350 rd = self.rd.num
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351 rn = self.rn.num
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352 imm3 = self.imm3.imm
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353 opcode = self.opcode
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354 h = (opcode << 11) | (1 << 10) | (imm3 << 6) | (rn << 3) | rd
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355 return u16(h)
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356
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219
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357 class regregreg_base(ArmInstruction):
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358 """ ??? Rd, Rn, Rm """
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359 operands = (Reg8Op, Reg8Op, Reg8Op)
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360 def __init__(self, rd, rn, rm):
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361 self.rd = rd
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362 self.rn = rn
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363 self.rm = rm
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364 def encode(self):
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365 rd = self.rd.num
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366 rn = self.rn.num
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367 rm = self.rm.num
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368 h = (self.opcode << 9) | (rm << 6) | (rn << 3) | rd
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369 return u16(h)
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370 def __repr__(self):
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371 return '{} {}, {}, {}'.format(self.mnemonic, self.rd, self.rn, self.rm)
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372
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373 @armtarget.instruction
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374 class addregs_ins(regregreg_base):
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375 mnemonic = 'ADD'
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376 opcode = 0b0001100
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377
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378 @armtarget.instruction
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379 class subregs_ins(regregreg_base):
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380 mnemonic = 'SUB'
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381 opcode = 0b0001101
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382
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383 class regreg_base(ArmInstruction):
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384 """ ??? Rdn, Rm """
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385 operands = (Reg8Op, Reg8Op)
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386 def __init__(self, rdn, rm):
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387 self.rdn = rdn
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388 self.rm = rm
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389 def encode(self):
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390 rdn = self.rdn.num
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391 rm = self.rm.num
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392 h = (self.opcode << 6) | (rm << 3) | rdn
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393 return u16(h)
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394 def __repr__(self):
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395 return '{} {}, {}'.format(self.mnemonic, self.rdn, self.rm)
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396
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397 @armtarget.instruction
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398 class andregs_ins(regreg_base):
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399 mnemonic = 'AND'
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400 opcode = 0b0100000000
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401
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402 @armtarget.instruction
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403 class orrregs_ins(regreg_base):
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404 mnemonic = 'ORR'
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405 opcode = 0b0100001100
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406
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407 @armtarget.instruction
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408 class cmp_ins(regreg_base):
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409 mnemonic = 'CMP'
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410 opcode = 0b0100001010
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411
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203
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412 @armtarget.instruction
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413 class cmpregimm8_ins(ArmInstruction):
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414 """ cmp Rn, imm8 """
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415 mnemonic = 'cmp'
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416 opcode = 5 # 00101
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417 operands = (RegOp, Imm8)
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418 def __init__(self, rn, imm):
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419 self.rn = rn
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420 self.imm = imm
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421 def encode(self):
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422 rn = self.rn.num
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423 imm = self.imm.imm
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424 opcode = self.opcode
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425 h = (opcode << 11) | (rn << 8) | imm
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426 return u16(h)
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202
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427
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219
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428 # Jumping:
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218
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429
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430 @armtarget.instruction
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205
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431 class jmp_ins(ArmInstruction):
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219
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432 operands = (ALabel,)
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205
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433 mnemonic = 'jmp'
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434 def __init__(self, target_label):
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219
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435 assert type(target_label) is ALabel
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205
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436 self.target = target_label
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437 def fixUp(self):
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438 pass
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439 def encode(self):
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219
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440 h = 0 # TODO
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205
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441 return u16(h)
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219
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442 def __repr__(self):
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443 return 'B {0}'.format(self.target.name)
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444
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445 @armtarget.instruction
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446 class beq_ins(ArmInstruction):
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447 operands = (ALabel,)
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448 mnemonic = 'beq'
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449 def __init__(self, target_label):
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450 assert type(target_label) is ALabel
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451 self.target = target_label
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452 def fixUp(self):
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453 pass
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454 def encode(self):
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455 h = 0 # TODO
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456 return u16(h)
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457 def __repr__(self):
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458 return 'BEQ {0}'.format(self.target.name)
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205
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459
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460 @armtarget.instruction
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461 class push_ins(ArmInstruction):
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206
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462 operands = (RegisterSet,)
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205
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463 mnemonic = 'push'
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464 def __init__(self, regs):
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206
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465 assert (type(regs),) == self.operands, (type(regs),)
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205
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466 self.regs = regs
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206
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467 def __repr__(self):
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468 return '{0} {{{1}}}'.format(self.mnemonic, self.regs)
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205
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469 def encode(self):
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206
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470 reg_list = 0
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471 M = 0
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472 for n in self.regs.registerNumbers():
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473 if n < 8:
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474 reg_list |= (1 << n)
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475 elif n == 14:
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476 M = 1
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477 else:
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478 raise NotImplementedError('not implemented for this register')
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479 h = (0x5a << 9) | (M << 8) | reg_list
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480 return u16(h)
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205
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481
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482 @armtarget.instruction
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483 class pop_ins(ArmInstruction):
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206
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484 operands = (RegisterSet,)
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205
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485 mnemonic = 'pop'
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486 def __init__(self, regs):
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487 self.regs = regs
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207
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488 def __repr__(self):
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489 return '{0} {{{1}}}'.format(self.mnemonic, self.regs)
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205
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490 def encode(self):
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206
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491 reg_list = 0
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492 P = 0
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493 for n in self.regs.registerNumbers():
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494 if n < 8:
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495 reg_list |= (1 << n)
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496 elif n == 15:
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497 P = 1
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498 else:
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499 raise NotImplementedError('not implemented for this register')
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500 h = (0x5E << 9) | (P << 8) | reg_list
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501 return u16(h)
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205
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502
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503 @armtarget.instruction
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202
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504 class yield_ins(ArmInstruction):
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505 operands = ()
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506 mnemonic = 'yield'
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507 def encode(self):
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508 return u16(0xbf10)
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509
|
|
206
|
510 armtarget.check()
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511
|
