--- a/python/cortexm3.py	Tue Jul 09 17:59:15 2013 +0200
+++ b/python/cortexm3.py	Thu Jul 11 07:42:30 2013 +0200
@@ -101,7 +101,7 @@
 class MemPcRel(MemRegXRel):
     regname = 'PC'
 
-class MemoryOpReg8Imm5:
+class MemR8Rel:
     def __init__(self, basereg, offset):
         assert type(basereg) is ArmReg
         self.basereg = basereg
@@ -212,19 +212,19 @@
 
 class LS_imm5_base(ArmInstruction):
     """ ??? Rt, [Rn, imm5] """
-    operands = (Reg8Op, MemoryOpReg8Imm5)
+    operands = (Reg8Op, MemR8Rel)
     def __init__(self, rt, memop):
         assert memop.offset % 4 == 0
         self.imm5 = memop.offset >> 2
         self.rn = memop.basereg.num
-        self.rt = rt.num
+        self.rt = rt
         self.memloc = memop
         assert self.rn < 8
-        assert self.rt < 8
+        assert self.rt.num < 8
 
     def encode(self):
         Rn = self.rn
-        Rt = self.rt
+        Rt = self.rt.num
         imm5 = self.imm5
 
         h = (self.opcode << 11) | (imm5 << 6) | (Rn << 3) | Rt
@@ -252,7 +252,6 @@
         rt = self.rt.num
         assert rt < 8
         imm8 = self.offset >> 2
-        print(imm8)
         assert imm8 < 256
         h = (self.opcode << 8) | (rt << 8) | imm8
         return u16(h)