--- a/python/cortexm3.py	Sat Sep 14 17:29:10 2013 +0200
+++ b/python/cortexm3.py	Mon Sep 16 21:51:17 2013 +0200
@@ -111,7 +111,7 @@
 
     @classmethod
     def Create(cls, vop):
-        if type(vop) is AUnop and vop.operation == '[]':
+        if type(vop) is AUnop and vop.operation == '[]' and type(vop.arg) is ABinop and vop.arg.op == '+':
             vop = vop.arg # descent
             offset = isRegOffset(cls.regname, vop.arg1, vop.arg2)
             if type(offset) is int:
@@ -121,11 +121,10 @@
             elif type(vop) is ASymbol and vop.name.upper() == self.regname:
                 return cls(0)
 
+
 class MemSpRel(MemRegXRel):
     regname = 'SP'
 
-class MemPcRel(MemRegXRel):
-    regname = 'PC'
 
 class MemR8Rel:
     def __init__(self, basereg, offset):
@@ -163,8 +162,10 @@
     def __init__(self, regs):
         assert type(regs) is set
         self.regs = regs
+
     def __repr__(self):
         return ','.join([str(r) for r in self.regs])
+
     @classmethod
     def Create(cls, vop):
         assert type(vop) is AUnop and vop.operation == '{}'
@@ -218,6 +219,7 @@
 pc = ArmReg(15, 'pc')
 armtarget.registers.append(pc)
 
+
 class ArmInstruction(Instruction):
     pass
 
@@ -307,7 +309,7 @@
 
 @armtarget.instruction
 class ldr_pcrel(ArmInstruction):
-    """ ldr Rt, [PC, imm8], store value into memory """
+    """ ldr Rt, LABEL, load value from pc relative position """
     mnemonic = 'ldr'
     operands = (RegOp, LabelRef)
     def __init__(self, rt, label):
@@ -374,13 +376,8 @@
 
 
 
-@armtarget.instruction
-class addregregimm3_ins(ArmInstruction):
-    """ add Rd, Rn, imm3 """
-    mnemonic = 'add'
-    opcode = 3 # 00011
-    operands = (RegOp, RegOp, Imm3)
-    irpattern = 3
+class regregimm3_base(ArmInstruction):
+    operands = (Reg8Op, Reg8Op, Imm3)
     def __init__(self, rd, rn, imm3):
         self.rd = rd
         self.rn = rn
@@ -390,9 +387,24 @@
         rn = self.rn.num
         imm3 = self.imm3.imm
         opcode = self.opcode
-        h = (opcode << 11) | (1 << 10) | (imm3 << 6) | (rn << 3) | rd
+        h = (self.opcode << 9) | (imm3 << 6) | (rn << 3) | rd
         return u16(h)
 
+
+@armtarget.instruction
+class addregregimm3_ins(regregimm3_base):
+    """ add Rd, Rn, imm3 """
+    mnemonic = 'add'
+    opcode = 0b0001110
+
+
+@armtarget.instruction
+class subregregimm3_ins(regregimm3_base):
+    """ sub Rd, Rn, imm3 """
+    mnemonic = 'sub'
+    opcode = 0b0001111
+
+
 class regregreg_base(ArmInstruction):
     """ ??? Rd, Rn, Rm """
     operands = (Reg8Op, Reg8Op, Reg8Op)
@@ -437,6 +449,22 @@
         return '{} {}, {}'.format(self.mnemonic, self.rd, self.rm)
         
 
+@armtarget.instruction
+class mulregreg_ins(ArmInstruction):
+    """ mul Rn, Rdm """
+    operands = (Reg8Op, Reg8Op)
+    mnemonic = 'mul'
+    def __init__(self, rn, rdm):
+        self.rn = rn
+        self.rdm = rdm
+    def encode(self):
+        rn = self.rn.num
+        rdm = self.rdm.num
+        opcode = 0b0100001101
+        h = (opcode << 6) | (rn << 3) | rdm
+        return u16(h)
+    def __repr__(self):
+        return '{} {}, {}'.format(self.mnemonic, self.rdn, self.rm)
 
 class regreg_base(ArmInstruction):
     """ ??? Rdn, Rm """