--- a/python/cortexm3.py	Wed Sep 04 17:35:06 2013 +0200
+++ b/python/cortexm3.py	Sat Sep 14 17:29:10 2013 +0200
@@ -1,11 +1,12 @@
 import struct
 import types
-from target import Register, Instruction, Target, Imm8, Label, Imm3, LabelRef, Imm32
+from target import Register, Instruction, Target, Imm8, Label, Imm3, LabelRef, Imm32, Imm7
 from asmnodes import ASymbol, ANumber, AUnop, ABinop
 from ppci import CompilerError
 import ir
 
 # TODO: encode this in DSL (domain specific language)
+# TBD: is this required?
 
 def u16(h):
     return struct.pack('<H', h)
@@ -55,6 +56,30 @@
                 if r.num < 8:
                     return cls(r.num)
 
+class Reg16Op:
+    def __init__(self, num):
+        assert num < 16
+        self.num = num
+
+    @classmethod
+    def Create(cls, vop):
+        if type(vop) is ASymbol:
+            name = vop.name
+            regs = {}
+            for r in armtarget.registers:
+                regs[r.name] = r
+            if name in regs:
+                r = regs[name]
+                if r.num < 16:
+                    return cls(r.num)
+
+class RegSpOp:
+    @classmethod
+    def Create(cls, vop):
+        if type(vop) is ASymbol:
+            if vop.name.lower() == 'sp':
+                return cls()
+
 def getRegNum(n):
     for r in armtarget.registers:
         if r.num == n:
@@ -244,6 +269,7 @@
 
         h = (self.opcode << 11) | (imm5 << 6) | (Rn << 3) | Rt
         return u16(h)
+
     def __repr__(self):
         return '{} {}, {}'.format(self.mnemonic, self.rt, self.memloc)
 
@@ -346,6 +372,8 @@
 
 # Arithmatics:
 
+
+
 @armtarget.instruction
 class addregregimm3_ins(ArmInstruction):
     """ add Rd, Rn, imm3 """
@@ -391,6 +419,25 @@
     mnemonic = 'SUB'
     opcode = 0b0001101
 
+
+@armtarget.instruction
+class movregreg_ext_ins(ArmInstruction):
+    operands = (Reg16Op, Reg16Op)
+    mnemonic = 'MOV'
+    def __init__(self, rd, rm):
+        self.rd = rd
+        self.rm = rm
+    def encode(self):
+        Rd = self.rd.num & 0x7
+        D = (self.rd.num >> 3) & 0x1
+        Rm = self.rm.num
+        opcode = 0b01000110
+        return u16((opcode << 8) | (D << 7) |(Rm << 3) | Rd)
+    def __repr__(self):
+        return '{} {}, {}'.format(self.mnemonic, self.rd, self.rm)
+        
+
+
 class regreg_base(ArmInstruction):
     """ ??? Rdn, Rm """
     operands = (Reg8Op, Reg8Op)
@@ -575,5 +622,32 @@
     def encode(self):
         return u16(0xbf10)
 
+# misc:
+
+# add/sub SP:
+@armtarget.instruction
+class addspsp_ins(ArmInstruction):
+    operands = (RegSpOp, RegSpOp, Imm7)
+    mnemonic = 'add'
+    def __init__(self, _sp, _sp2, imm7):
+        self.imm7 = imm7.imm
+        assert self.imm7 % 4 == 0
+        self.imm7 >>= 2
+
+    def encode(self):
+        return u16((0b101100000 << 7) |self.imm7)
+
+@armtarget.instruction
+class subspsp_ins(ArmInstruction):
+    operands = (RegSpOp, RegSpOp, Imm7)
+    mnemonic = 'sub'
+    def __init__(self, _sp, _sp2, imm7):
+        self.imm7 = imm7.imm
+        assert self.imm7 % 4 == 0
+        self.imm7 >>= 2
+
+    def encode(self):
+        return u16((0b101100001 << 7) |self.imm7)
+
 armtarget.check()