|
205
|
1 import struct, types
|
|
206
|
2 from target import Register, Instruction, Target, Imm8, Label, Imm3
|
|
234
|
3 from asmnodes import ASymbol, ANumber, AUnop, ABinop
|
|
202
|
4 from ppci import CompilerError
|
|
205
|
5 import ir
|
|
202
|
6
|
|
218
|
7 # TODO: encode this in DSL (domain specific language)
|
|
|
8
|
|
202
|
9 def u16(h):
|
|
|
10 return struct.pack('<H', h)
|
|
|
11
|
|
205
|
12 def u32(x):
|
|
|
13 return struct.pack('<I', x)
|
|
|
14
|
|
202
|
15 armtarget = Target('arm')
|
|
|
16
|
|
|
17 class ArmReg(Register):
|
|
|
18 def __init__(self, num, name):
|
|
|
19 super().__init__(name)
|
|
|
20 self.num = num
|
|
206
|
21 def __repr__(self):
|
|
|
22 return self.name
|
|
202
|
23
|
|
203
|
24 class RegOp:
|
|
|
25 def __init__(self, num):
|
|
206
|
26 assert num < 16
|
|
203
|
27 self.num = num
|
|
|
28
|
|
|
29 @classmethod
|
|
|
30 def Create(cls, vop):
|
|
|
31 if type(vop) is ASymbol:
|
|
|
32 name = vop.name
|
|
|
33 regs = {}
|
|
|
34 for r in armtarget.registers:
|
|
|
35 regs[r.name] = r
|
|
|
36 if name in regs:
|
|
|
37 r = regs[name]
|
|
|
38 return cls(r.num)
|
|
234
|
39
|
|
219
|
40 class Reg8Op:
|
|
|
41 def __init__(self, num):
|
|
|
42 assert num < 8
|
|
|
43 self.num = num
|
|
|
44
|
|
|
45 @classmethod
|
|
|
46 def Create(cls, vop):
|
|
|
47 if type(vop) is ASymbol:
|
|
|
48 name = vop.name
|
|
|
49 regs = {}
|
|
|
50 for r in armtarget.registers:
|
|
|
51 regs[r.name] = r
|
|
|
52 if name in regs:
|
|
|
53 r = regs[name]
|
|
|
54 if r.num < 8:
|
|
|
55 return cls(r.num)
|
|
203
|
56
|
|
206
|
57 def getRegNum(n):
|
|
|
58 for r in armtarget.registers:
|
|
|
59 if r.num == n:
|
|
|
60 return r
|
|
203
|
61
|
|
206
|
62 def getRegisterRange(n1, n2):
|
|
|
63 regs = []
|
|
|
64 if n1.num < n2.num:
|
|
|
65 for n in range(n1.num, n2.num + 1):
|
|
|
66 r = getRegNum(n)
|
|
|
67 assert r
|
|
|
68 regs.append(r)
|
|
|
69 return regs
|
|
203
|
70
|
|
224
|
71 def isRegOffset(regname, x, y):
|
|
|
72 if type(x) is ASymbol and type(y) is ANumber and x.name.upper() == regname:
|
|
|
73 return y.number
|
|
|
74 elif type(y) is ASymbol and type(x) is ANumber and y.name.upper() == regname:
|
|
|
75 return x.number
|
|
|
76
|
|
|
77
|
|
|
78 class MemRegXRel:
|
|
|
79 def __init__(self, offset):
|
|
|
80 assert offset % 4 == 0
|
|
212
|
81 self.offset = offset
|
|
|
82
|
|
219
|
83 def __repr__(self):
|
|
224
|
84 return '[{}, #{}]'.format(self.regname, self.offset)
|
|
219
|
85
|
|
212
|
86 @classmethod
|
|
|
87 def Create(cls, vop):
|
|
|
88 if type(vop) is AUnop and vop.operation == '[]':
|
|
|
89 vop = vop.arg # descent
|
|
224
|
90 offset = isRegOffset(cls.regname, vop.arg1, vop.arg2)
|
|
|
91 if type(offset) is int:
|
|
|
92 if offset % 4 == 0:
|
|
223
|
93 offset = vop.arg2.number
|
|
|
94 return cls(offset)
|
|
224
|
95 elif type(vop) is ASymbol and vop.name.upper() == self.regname:
|
|
223
|
96 return cls(0)
|
|
|
97
|
|
224
|
98 class MemSpRel(MemRegXRel):
|
|
|
99 regname = 'SP'
|
|
|
100
|
|
|
101 class MemPcRel(MemRegXRel):
|
|
|
102 regname = 'PC'
|
|
|
103
|
|
225
|
104 class MemR8Rel:
|
|
219
|
105 def __init__(self, basereg, offset):
|
|
|
106 assert type(basereg) is ArmReg
|
|
|
107 self.basereg = basereg
|
|
|
108 self.offset = offset
|
|
|
109
|
|
|
110 def __repr__(self):
|
|
|
111 return '[{}, #{}]'.format(self.basereg, self.offset)
|
|
|
112
|
|
|
113 @classmethod
|
|
|
114 def Create(cls, vop):
|
|
|
115 if type(vop) is AUnop and vop.operation == '[]':
|
|
|
116 vop = vop.arg # descent
|
|
|
117 if type(vop) is ABinop:
|
|
|
118 if vop.op == '+' and type(vop.arg1) is ASymbol and type(vop.arg2) is ANumber:
|
|
|
119 offset = vop.arg2.number
|
|
|
120 if offset > 120:
|
|
|
121 return
|
|
|
122 basereg = Reg8Op.Create(vop.arg1)
|
|
|
123 if not basereg:
|
|
|
124 return
|
|
|
125 else:
|
|
|
126 return
|
|
|
127 elif type(vop) is ASymbol:
|
|
|
128 offset = 0
|
|
|
129 basereg = Reg8Op.Create(vop)
|
|
|
130 if not basereg:
|
|
|
131 return
|
|
|
132 else:
|
|
|
133 return
|
|
|
134 return cls(getRegNum(basereg.num), offset)
|
|
212
|
135
|
|
205
|
136 class RegisterSet:
|
|
|
137 def __init__(self, regs):
|
|
206
|
138 assert type(regs) is set
|
|
|
139 self.regs = regs
|
|
|
140 def __repr__(self):
|
|
|
141 return ','.join([str(r) for r in self.regs])
|
|
|
142 @classmethod
|
|
|
143 def Create(cls, vop):
|
|
|
144 assert type(vop) is AUnop and vop.operation == '{}'
|
|
|
145 assert type(vop.arg) is list
|
|
|
146 regs = set()
|
|
|
147 for arg in vop.arg:
|
|
|
148 if type(arg) is ASymbol:
|
|
|
149 reg = RegOp.Create(arg)
|
|
|
150 if not reg:
|
|
|
151 return
|
|
|
152 regs.add(reg)
|
|
|
153 elif type(arg) is ABinop and arg.op == '-':
|
|
|
154 reg1 = RegOp.Create(arg.arg1)
|
|
|
155 reg2 = RegOp.Create(arg.arg2)
|
|
|
156 if not reg1:
|
|
|
157 return
|
|
|
158 if not reg2:
|
|
|
159 return
|
|
|
160 for r in getRegisterRange(reg1, reg2):
|
|
|
161 regs.add(r)
|
|
|
162 else:
|
|
|
163 raise Exception('Cannot be')
|
|
|
164 return cls(regs)
|
|
|
165
|
|
|
166 def registerNumbers(self):
|
|
|
167 return [r.num for r in self.regs]
|
|
205
|
168
|
|
202
|
169 # 8 bit registers:
|
|
205
|
170 r0 = ArmReg(0, 'r0')
|
|
|
171 armtarget.registers.append(r0)
|
|
206
|
172 r1 = ArmReg(1, 'r1')
|
|
|
173 armtarget.registers.append(r1)
|
|
|
174 r2 = ArmReg(2, 'r2')
|
|
|
175 armtarget.registers.append(r2)
|
|
|
176 r3 = ArmReg(3, 'r3')
|
|
|
177 armtarget.registers.append(r3)
|
|
202
|
178 r4 = ArmReg(4, 'r4')
|
|
|
179 armtarget.registers.append(r4)
|
|
203
|
180 r5 = ArmReg(5, 'r5')
|
|
|
181 armtarget.registers.append(r5)
|
|
|
182 r6 = ArmReg(6, 'r6')
|
|
|
183 armtarget.registers.append(r6)
|
|
|
184 r7 = ArmReg(7, 'r7')
|
|
|
185 armtarget.registers.append(r7)
|
|
206
|
186 # Other registers:
|
|
|
187 # TODO
|
|
|
188 sp = ArmReg(13, 'sp')
|
|
|
189 armtarget.registers.append(sp)
|
|
|
190 lr = ArmReg(14, 'lr')
|
|
|
191 armtarget.registers.append(lr)
|
|
|
192 pc = ArmReg(15, 'pc')
|
|
|
193 armtarget.registers.append(pc)
|
|
202
|
194
|
|
|
195 class ArmInstruction(Instruction):
|
|
|
196 pass
|
|
|
197
|
|
205
|
198 class dcd_ins(ArmInstruction):
|
|
|
199 mnemonic = 'dcd'
|
|
|
200 def __init__(self, expr):
|
|
|
201 self.expr = expr
|
|
219
|
202
|
|
205
|
203 def encode(self):
|
|
|
204 return u32(self.expr)
|
|
202
|
205
|
|
219
|
206 def __repr__(self):
|
|
|
207 return 'DCD 0x{0:X}'.format(self.expr)
|
|
|
208
|
|
|
209
|
|
|
210
|
|
|
211 # Memory related
|
|
|
212
|
|
|
213 class LS_imm5_base(ArmInstruction):
|
|
|
214 """ ??? Rt, [Rn, imm5] """
|
|
225
|
215 operands = (Reg8Op, MemR8Rel)
|
|
212
|
216 def __init__(self, rt, memop):
|
|
|
217 assert memop.offset % 4 == 0
|
|
|
218 self.imm5 = memop.offset >> 2
|
|
|
219 self.rn = memop.basereg.num
|
|
225
|
220 self.rt = rt
|
|
219
|
221 self.memloc = memop
|
|
|
222 assert self.rn < 8
|
|
225
|
223 assert self.rt.num < 8
|
|
212
|
224
|
|
|
225 def encode(self):
|
|
|
226 Rn = self.rn
|
|
225
|
227 Rt = self.rt.num
|
|
212
|
228 imm5 = self.imm5
|
|
219
|
229
|
|
|
230 h = (self.opcode << 11) | (imm5 << 6) | (Rn << 3) | Rt
|
|
|
231 return u16(h)
|
|
|
232 def __repr__(self):
|
|
|
233 return '{} {}, {}'.format(self.mnemonic, self.rt, self.memloc)
|
|
|
234
|
|
|
235 @armtarget.instruction
|
|
|
236 class storeimm5_ins(LS_imm5_base):
|
|
|
237 mnemonic = 'STR'
|
|
|
238 opcode = 0xC
|
|
|
239
|
|
|
240 @armtarget.instruction
|
|
|
241 class loadimm5_ins(LS_imm5_base):
|
|
|
242 mnemonic = 'LDR'
|
|
|
243 opcode = 0xD
|
|
|
244
|
|
|
245 class ls_sp_base_imm8(ArmInstruction):
|
|
224
|
246 operands = (Reg8Op, MemSpRel)
|
|
219
|
247 def __init__(self, rt, memop):
|
|
|
248 self.rt = rt
|
|
|
249 self.offset = memop.offset
|
|
|
250
|
|
|
251 def encode(self):
|
|
|
252 rt = self.rt.num
|
|
|
253 assert rt < 8
|
|
|
254 imm8 = self.offset >> 2
|
|
|
255 assert imm8 < 256
|
|
|
256 h = (self.opcode << 8) | (rt << 8) | imm8
|
|
212
|
257 return u16(h)
|
|
|
258
|
|
219
|
259 def __repr__(self):
|
|
|
260 return '{} {}, [sp,#{}]'.format(self.mnemonic, self.rt, self.offset)
|
|
|
261
|
|
212
|
262 @armtarget.instruction
|
|
219
|
263 class ldr_pcrel(ArmInstruction):
|
|
|
264 """ ldr Rt, [PC, imm8], store value into memory """
|
|
212
|
265 mnemonic = 'ldr'
|
|
224
|
266 operands = (RegOp, MemPcRel)
|
|
219
|
267 def __init__(self, rt, label):
|
|
|
268 self.rt = rt
|
|
|
269 self.label = label
|
|
|
270 self.offset = 0
|
|
212
|
271
|
|
234
|
272 def resolve(self, f):
|
|
|
273 la = f(self.label)
|
|
|
274 self.offset = (la - self.address) + 4
|
|
|
275
|
|
212
|
276 def encode(self):
|
|
219
|
277 rt = self.rt.num
|
|
|
278 assert rt < 8
|
|
|
279 imm8 = self.offset >> 2
|
|
|
280 assert imm8 < 256
|
|
|
281 h = (0x9 << 11) | (rt << 8) | imm8
|
|
212
|
282 return u16(h)
|
|
|
283
|
|
219
|
284 def __repr__(self):
|
|
232
|
285 return 'LDR {}, {}'.format(self.rt, self.label.name)
|
|
219
|
286
|
|
|
287 @armtarget.instruction
|
|
|
288 class ldr_sprel(ls_sp_base_imm8):
|
|
|
289 """ ldr Rt, [SP, imm8] """
|
|
|
290 mnemonic = 'LDR'
|
|
|
291 opcode = 0x98
|
|
|
292
|
|
|
293 @armtarget.instruction
|
|
|
294 class str_sprel(ls_sp_base_imm8):
|
|
|
295 """ str Rt, [SP, imm8] """
|
|
|
296 mnemonic = 'STR'
|
|
|
297 opcode = 0x90
|
|
|
298
|
|
212
|
299 @armtarget.instruction
|
|
202
|
300 class mov_ins(ArmInstruction):
|
|
|
301 """ mov Rd, imm8, move immediate value into register """
|
|
|
302 mnemonic = 'mov'
|
|
203
|
303 opcode = 4 # 00100 Rd(3) imm8
|
|
|
304 operands = (RegOp, Imm8)
|
|
205
|
305 irpattern = ir.ImmLoad
|
|
203
|
306 def __init__(self, rd, imm):
|
|
|
307 self.imm = imm.imm
|
|
|
308 self.r = rd.num
|
|
205
|
309
|
|
202
|
310 def encode(self):
|
|
|
311 rd = self.r
|
|
|
312 opcode = self.opcode
|
|
|
313 imm8 = self.imm
|
|
|
314 h = (opcode << 11) | (rd << 8) | imm8
|
|
|
315 return u16(h)
|
|
219
|
316 def __repr__(self):
|
|
|
317 return 'MOV {0}, xx?'.format(self.r)
|
|
232
|
318
|
|
|
319
|
|
203
|
320 @armtarget.instruction
|
|
|
321 class movregreg_ins(ArmInstruction):
|
|
|
322 """ mov Rd, Rm """
|
|
|
323 mnemonic = 'mov'
|
|
|
324 operands = (RegOp, RegOp)
|
|
|
325 def __init__(self, rd, rm):
|
|
|
326 self.rd = rd
|
|
|
327 self.rm = rm
|
|
|
328 def encode(self):
|
|
|
329 rd = self.rd.num
|
|
|
330 D = (rd & 0x8) >> 3
|
|
|
331 assert D < 2
|
|
|
332 rd = rd & 0x7
|
|
|
333 rm = self.rm.num
|
|
|
334 assert rm < 16
|
|
|
335 opcode = self.opcode
|
|
219
|
336 h = (1 << 14) | (3 << 9) | (D << 7) | (rm << 3) | rd
|
|
203
|
337 return u16(h)
|
|
|
338
|
|
219
|
339
|
|
|
340
|
|
|
341 # Arithmatics:
|
|
|
342
|
|
203
|
343 @armtarget.instruction
|
|
|
344 class addregregimm3_ins(ArmInstruction):
|
|
|
345 """ add Rd, Rn, imm3 """
|
|
|
346 mnemonic = 'add'
|
|
|
347 opcode = 3 # 00011
|
|
|
348 operands = (RegOp, RegOp, Imm3)
|
|
205
|
349 irpattern = 3
|
|
203
|
350 def __init__(self, rd, rn, imm3):
|
|
|
351 self.rd = rd
|
|
|
352 self.rn = rn
|
|
|
353 self.imm3 = imm3
|
|
|
354 def encode(self):
|
|
|
355 rd = self.rd.num
|
|
|
356 rn = self.rn.num
|
|
|
357 imm3 = self.imm3.imm
|
|
|
358 opcode = self.opcode
|
|
|
359 h = (opcode << 11) | (1 << 10) | (imm3 << 6) | (rn << 3) | rd
|
|
|
360 return u16(h)
|
|
|
361
|
|
219
|
362 class regregreg_base(ArmInstruction):
|
|
|
363 """ ??? Rd, Rn, Rm """
|
|
|
364 operands = (Reg8Op, Reg8Op, Reg8Op)
|
|
|
365 def __init__(self, rd, rn, rm):
|
|
|
366 self.rd = rd
|
|
|
367 self.rn = rn
|
|
|
368 self.rm = rm
|
|
|
369 def encode(self):
|
|
|
370 rd = self.rd.num
|
|
|
371 rn = self.rn.num
|
|
|
372 rm = self.rm.num
|
|
|
373 h = (self.opcode << 9) | (rm << 6) | (rn << 3) | rd
|
|
|
374 return u16(h)
|
|
|
375 def __repr__(self):
|
|
|
376 return '{} {}, {}, {}'.format(self.mnemonic, self.rd, self.rn, self.rm)
|
|
|
377
|
|
|
378 @armtarget.instruction
|
|
|
379 class addregs_ins(regregreg_base):
|
|
|
380 mnemonic = 'ADD'
|
|
|
381 opcode = 0b0001100
|
|
|
382
|
|
|
383 @armtarget.instruction
|
|
|
384 class subregs_ins(regregreg_base):
|
|
|
385 mnemonic = 'SUB'
|
|
|
386 opcode = 0b0001101
|
|
|
387
|
|
|
388 class regreg_base(ArmInstruction):
|
|
|
389 """ ??? Rdn, Rm """
|
|
|
390 operands = (Reg8Op, Reg8Op)
|
|
|
391 def __init__(self, rdn, rm):
|
|
|
392 self.rdn = rdn
|
|
|
393 self.rm = rm
|
|
|
394 def encode(self):
|
|
|
395 rdn = self.rdn.num
|
|
|
396 rm = self.rm.num
|
|
|
397 h = (self.opcode << 6) | (rm << 3) | rdn
|
|
|
398 return u16(h)
|
|
|
399 def __repr__(self):
|
|
|
400 return '{} {}, {}'.format(self.mnemonic, self.rdn, self.rm)
|
|
|
401
|
|
|
402 @armtarget.instruction
|
|
|
403 class andregs_ins(regreg_base):
|
|
|
404 mnemonic = 'AND'
|
|
|
405 opcode = 0b0100000000
|
|
|
406
|
|
|
407 @armtarget.instruction
|
|
|
408 class orrregs_ins(regreg_base):
|
|
|
409 mnemonic = 'ORR'
|
|
|
410 opcode = 0b0100001100
|
|
|
411
|
|
|
412 @armtarget.instruction
|
|
|
413 class cmp_ins(regreg_base):
|
|
|
414 mnemonic = 'CMP'
|
|
|
415 opcode = 0b0100001010
|
|
|
416
|
|
203
|
417 @armtarget.instruction
|
|
232
|
418 class lslregs_ins(regreg_base):
|
|
|
419 mnemonic = 'LSL'
|
|
|
420 opcode = 0b0100000010
|
|
|
421
|
|
|
422 @armtarget.instruction
|
|
203
|
423 class cmpregimm8_ins(ArmInstruction):
|
|
|
424 """ cmp Rn, imm8 """
|
|
|
425 mnemonic = 'cmp'
|
|
|
426 opcode = 5 # 00101
|
|
|
427 operands = (RegOp, Imm8)
|
|
|
428 def __init__(self, rn, imm):
|
|
|
429 self.rn = rn
|
|
|
430 self.imm = imm
|
|
|
431 def encode(self):
|
|
|
432 rn = self.rn.num
|
|
|
433 imm = self.imm.imm
|
|
|
434 opcode = self.opcode
|
|
|
435 h = (opcode << 11) | (rn << 8) | imm
|
|
|
436 return u16(h)
|
|
202
|
437
|
|
219
|
438 # Jumping:
|
|
218
|
439
|
|
|
440 @armtarget.instruction
|
|
205
|
441 class jmp_ins(ArmInstruction):
|
|
219
|
442 operands = (ALabel,)
|
|
205
|
443 mnemonic = 'jmp'
|
|
|
444 def __init__(self, target_label):
|
|
219
|
445 assert type(target_label) is ALabel
|
|
205
|
446 self.target = target_label
|
|
|
447 def fixUp(self):
|
|
|
448 pass
|
|
|
449 def encode(self):
|
|
219
|
450 h = 0 # TODO
|
|
205
|
451 return u16(h)
|
|
219
|
452 def __repr__(self):
|
|
|
453 return 'B {0}'.format(self.target.name)
|
|
|
454
|
|
|
455 @armtarget.instruction
|
|
|
456 class beq_ins(ArmInstruction):
|
|
|
457 operands = (ALabel,)
|
|
|
458 mnemonic = 'beq'
|
|
|
459 def __init__(self, target_label):
|
|
|
460 assert type(target_label) is ALabel
|
|
|
461 self.target = target_label
|
|
|
462 def fixUp(self):
|
|
|
463 pass
|
|
|
464 def encode(self):
|
|
|
465 h = 0 # TODO
|
|
|
466 return u16(h)
|
|
|
467 def __repr__(self):
|
|
|
468 return 'BEQ {0}'.format(self.target.name)
|
|
205
|
469
|
|
|
470 @armtarget.instruction
|
|
|
471 class push_ins(ArmInstruction):
|
|
206
|
472 operands = (RegisterSet,)
|
|
205
|
473 mnemonic = 'push'
|
|
|
474 def __init__(self, regs):
|
|
206
|
475 assert (type(regs),) == self.operands, (type(regs),)
|
|
205
|
476 self.regs = regs
|
|
206
|
477 def __repr__(self):
|
|
|
478 return '{0} {{{1}}}'.format(self.mnemonic, self.regs)
|
|
205
|
479 def encode(self):
|
|
206
|
480 reg_list = 0
|
|
|
481 M = 0
|
|
|
482 for n in self.regs.registerNumbers():
|
|
|
483 if n < 8:
|
|
|
484 reg_list |= (1 << n)
|
|
|
485 elif n == 14:
|
|
|
486 M = 1
|
|
|
487 else:
|
|
|
488 raise NotImplementedError('not implemented for this register')
|
|
|
489 h = (0x5a << 9) | (M << 8) | reg_list
|
|
|
490 return u16(h)
|
|
205
|
491
|
|
|
492 @armtarget.instruction
|
|
|
493 class pop_ins(ArmInstruction):
|
|
206
|
494 operands = (RegisterSet,)
|
|
205
|
495 mnemonic = 'pop'
|
|
|
496 def __init__(self, regs):
|
|
|
497 self.regs = regs
|
|
207
|
498 def __repr__(self):
|
|
|
499 return '{0} {{{1}}}'.format(self.mnemonic, self.regs)
|
|
205
|
500 def encode(self):
|
|
206
|
501 reg_list = 0
|
|
|
502 P = 0
|
|
|
503 for n in self.regs.registerNumbers():
|
|
|
504 if n < 8:
|
|
|
505 reg_list |= (1 << n)
|
|
|
506 elif n == 15:
|
|
|
507 P = 1
|
|
|
508 else:
|
|
|
509 raise NotImplementedError('not implemented for this register')
|
|
|
510 h = (0x5E << 9) | (P << 8) | reg_list
|
|
|
511 return u16(h)
|
|
205
|
512
|
|
|
513 @armtarget.instruction
|
|
202
|
514 class yield_ins(ArmInstruction):
|
|
|
515 operands = ()
|
|
|
516 mnemonic = 'yield'
|
|
|
517 def encode(self):
|
|
|
518 return u16(0xbf10)
|
|
|
519
|
|
206
|
520 armtarget.check()
|
|
|
521
|
