Mercurial > lcfOS
annotate python/cortexm3.py @ 275:6f2423df0675
Fixed serve arm-as
| author | Windel Bouwman |
|---|---|
| date | Sat, 14 Sep 2013 17:29:10 +0200 |
| parents | 5ec7580976d9 |
| children | 56d37ed4b4d2 |
| rev | line source |
|---|---|
| 261 | 1 import struct |
| 2 import types | |
| 275 | 3 from target import Register, Instruction, Target, Imm8, Label, Imm3, LabelRef, Imm32, Imm7 |
| 234 | 4 from asmnodes import ASymbol, ANumber, AUnop, ABinop |
| 202 | 5 from ppci import CompilerError |
| 205 | 6 import ir |
| 202 | 7 |
| 218 | 8 # TODO: encode this in DSL (domain specific language) |
| 275 | 9 # TBD: is this required? |
| 218 | 10 |
| 202 | 11 def u16(h): |
| 12 return struct.pack('<H', h) | |
| 13 | |
| 205 | 14 def u32(x): |
| 15 return struct.pack('<I', x) | |
| 16 | |
| 202 | 17 armtarget = Target('arm') |
| 18 | |
| 19 class ArmReg(Register): | |
| 20 def __init__(self, num, name): | |
| 21 super().__init__(name) | |
| 22 self.num = num | |
| 206 | 23 def __repr__(self): |
| 24 return self.name | |
| 202 | 25 |
| 203 | 26 class RegOp: |
| 27 def __init__(self, num): | |
| 206 | 28 assert num < 16 |
| 203 | 29 self.num = num |
| 30 | |
| 31 @classmethod | |
| 32 def Create(cls, vop): | |
| 33 if type(vop) is ASymbol: | |
| 34 name = vop.name | |
| 35 regs = {} | |
| 36 for r in armtarget.registers: | |
| 37 regs[r.name] = r | |
| 38 if name in regs: | |
| 39 r = regs[name] | |
| 40 return cls(r.num) | |
| 234 | 41 |
| 219 | 42 class Reg8Op: |
| 43 def __init__(self, num): | |
| 44 assert num < 8 | |
| 45 self.num = num | |
| 46 | |
| 47 @classmethod | |
| 48 def Create(cls, vop): | |
| 49 if type(vop) is ASymbol: | |
| 50 name = vop.name | |
| 51 regs = {} | |
| 52 for r in armtarget.registers: | |
| 53 regs[r.name] = r | |
| 54 if name in regs: | |
| 55 r = regs[name] | |
| 56 if r.num < 8: | |
| 57 return cls(r.num) | |
| 203 | 58 |
| 275 | 59 class Reg16Op: |
| 60 def __init__(self, num): | |
| 61 assert num < 16 | |
| 62 self.num = num | |
| 63 | |
| 64 @classmethod | |
| 65 def Create(cls, vop): | |
| 66 if type(vop) is ASymbol: | |
| 67 name = vop.name | |
| 68 regs = {} | |
| 69 for r in armtarget.registers: | |
| 70 regs[r.name] = r | |
| 71 if name in regs: | |
| 72 r = regs[name] | |
| 73 if r.num < 16: | |
| 74 return cls(r.num) | |
| 75 | |
| 76 class RegSpOp: | |
| 77 @classmethod | |
| 78 def Create(cls, vop): | |
| 79 if type(vop) is ASymbol: | |
| 80 if vop.name.lower() == 'sp': | |
| 81 return cls() | |
| 82 | |
| 206 | 83 def getRegNum(n): |
| 84 for r in armtarget.registers: | |
| 85 if r.num == n: | |
| 86 return r | |
| 203 | 87 |
| 206 | 88 def getRegisterRange(n1, n2): |
| 89 regs = [] | |
| 90 if n1.num < n2.num: | |
| 91 for n in range(n1.num, n2.num + 1): | |
| 92 r = getRegNum(n) | |
| 93 assert r | |
| 94 regs.append(r) | |
| 95 return regs | |
| 203 | 96 |
| 224 | 97 def isRegOffset(regname, x, y): |
| 98 if type(x) is ASymbol and type(y) is ANumber and x.name.upper() == regname: | |
| 99 return y.number | |
| 100 elif type(y) is ASymbol and type(x) is ANumber and y.name.upper() == regname: | |
| 101 return x.number | |
| 102 | |
| 103 | |
| 104 class MemRegXRel: | |
| 105 def __init__(self, offset): | |
| 106 assert offset % 4 == 0 | |
| 212 | 107 self.offset = offset |
| 108 | |
| 219 | 109 def __repr__(self): |
| 224 | 110 return '[{}, #{}]'.format(self.regname, self.offset) |
| 219 | 111 |
| 212 | 112 @classmethod |
| 113 def Create(cls, vop): | |
| 114 if type(vop) is AUnop and vop.operation == '[]': | |
| 115 vop = vop.arg # descent | |
| 224 | 116 offset = isRegOffset(cls.regname, vop.arg1, vop.arg2) |
| 117 if type(offset) is int: | |
| 118 if offset % 4 == 0: | |
| 223 | 119 offset = vop.arg2.number |
| 120 return cls(offset) | |
| 224 | 121 elif type(vop) is ASymbol and vop.name.upper() == self.regname: |
| 223 | 122 return cls(0) |
| 123 | |
| 224 | 124 class MemSpRel(MemRegXRel): |
| 125 regname = 'SP' | |
| 126 | |
| 127 class MemPcRel(MemRegXRel): | |
| 128 regname = 'PC' | |
| 129 | |
| 225 | 130 class MemR8Rel: |
| 219 | 131 def __init__(self, basereg, offset): |
| 132 assert type(basereg) is ArmReg | |
| 133 self.basereg = basereg | |
| 134 self.offset = offset | |
| 135 | |
| 136 def __repr__(self): | |
| 137 return '[{}, #{}]'.format(self.basereg, self.offset) | |
| 138 | |
| 139 @classmethod | |
| 140 def Create(cls, vop): | |
| 141 if type(vop) is AUnop and vop.operation == '[]': | |
| 142 vop = vop.arg # descent | |
| 143 if type(vop) is ABinop: | |
| 144 if vop.op == '+' and type(vop.arg1) is ASymbol and type(vop.arg2) is ANumber: | |
| 145 offset = vop.arg2.number | |
| 146 if offset > 120: | |
| 147 return | |
| 148 basereg = Reg8Op.Create(vop.arg1) | |
| 149 if not basereg: | |
| 150 return | |
| 151 else: | |
| 152 return | |
| 153 elif type(vop) is ASymbol: | |
| 154 offset = 0 | |
| 155 basereg = Reg8Op.Create(vop) | |
| 156 if not basereg: | |
| 157 return | |
| 158 else: | |
| 159 return | |
| 160 return cls(getRegNum(basereg.num), offset) | |
| 212 | 161 |
| 205 | 162 class RegisterSet: |
| 163 def __init__(self, regs): | |
| 206 | 164 assert type(regs) is set |
| 165 self.regs = regs | |
| 166 def __repr__(self): | |
| 167 return ','.join([str(r) for r in self.regs]) | |
| 168 @classmethod | |
| 169 def Create(cls, vop): | |
| 170 assert type(vop) is AUnop and vop.operation == '{}' | |
| 171 assert type(vop.arg) is list | |
| 172 regs = set() | |
| 173 for arg in vop.arg: | |
| 174 if type(arg) is ASymbol: | |
| 175 reg = RegOp.Create(arg) | |
| 176 if not reg: | |
| 177 return | |
| 178 regs.add(reg) | |
| 179 elif type(arg) is ABinop and arg.op == '-': | |
| 180 reg1 = RegOp.Create(arg.arg1) | |
| 181 reg2 = RegOp.Create(arg.arg2) | |
| 182 if not reg1: | |
| 183 return | |
| 184 if not reg2: | |
| 185 return | |
| 186 for r in getRegisterRange(reg1, reg2): | |
| 187 regs.add(r) | |
| 188 else: | |
| 189 raise Exception('Cannot be') | |
| 190 return cls(regs) | |
| 191 | |
| 192 def registerNumbers(self): | |
| 193 return [r.num for r in self.regs] | |
| 205 | 194 |
| 202 | 195 # 8 bit registers: |
| 205 | 196 r0 = ArmReg(0, 'r0') |
| 197 armtarget.registers.append(r0) | |
| 206 | 198 r1 = ArmReg(1, 'r1') |
| 199 armtarget.registers.append(r1) | |
| 200 r2 = ArmReg(2, 'r2') | |
| 201 armtarget.registers.append(r2) | |
| 202 r3 = ArmReg(3, 'r3') | |
| 203 armtarget.registers.append(r3) | |
| 202 | 204 r4 = ArmReg(4, 'r4') |
| 205 armtarget.registers.append(r4) | |
| 203 | 206 r5 = ArmReg(5, 'r5') |
| 207 armtarget.registers.append(r5) | |
| 208 r6 = ArmReg(6, 'r6') | |
| 209 armtarget.registers.append(r6) | |
| 210 r7 = ArmReg(7, 'r7') | |
| 211 armtarget.registers.append(r7) | |
| 206 | 212 # Other registers: |
| 213 # TODO | |
| 214 sp = ArmReg(13, 'sp') | |
| 215 armtarget.registers.append(sp) | |
| 216 lr = ArmReg(14, 'lr') | |
| 217 armtarget.registers.append(lr) | |
| 218 pc = ArmReg(15, 'pc') | |
| 219 armtarget.registers.append(pc) | |
| 202 | 220 |
| 221 class ArmInstruction(Instruction): | |
| 222 pass | |
| 223 | |
| 235 | 224 |
| 225 @armtarget.instruction | |
| 205 | 226 class dcd_ins(ArmInstruction): |
| 227 mnemonic = 'dcd' | |
| 235 | 228 operands = (Imm32,) |
| 205 | 229 def __init__(self, expr): |
| 237 | 230 if isinstance(expr, Imm32): |
| 231 self.expr = expr.imm | |
| 232 self.label = None | |
| 233 elif isinstance(expr, LabelRef): | |
| 234 self.expr = 0 | |
| 235 self.label = expr | |
| 236 else: | |
| 237 raise NotImplementedError() | |
| 238 | |
| 239 def resolve(self, f): | |
| 240 if self.label: | |
| 241 self.expr = f(self.label.name) | |
| 219 | 242 |
| 205 | 243 def encode(self): |
| 244 return u32(self.expr) | |
| 202 | 245 |
| 219 | 246 def __repr__(self): |
| 247 return 'DCD 0x{0:X}'.format(self.expr) | |
| 248 | |
| 249 | |
| 250 | |
| 251 # Memory related | |
| 252 | |
| 253 class LS_imm5_base(ArmInstruction): | |
| 254 """ ??? Rt, [Rn, imm5] """ | |
| 225 | 255 operands = (Reg8Op, MemR8Rel) |
| 212 | 256 def __init__(self, rt, memop): |
| 257 assert memop.offset % 4 == 0 | |
| 258 self.imm5 = memop.offset >> 2 | |
| 259 self.rn = memop.basereg.num | |
| 225 | 260 self.rt = rt |
| 219 | 261 self.memloc = memop |
| 262 assert self.rn < 8 | |
| 225 | 263 assert self.rt.num < 8 |
| 212 | 264 |
| 265 def encode(self): | |
| 266 Rn = self.rn | |
| 225 | 267 Rt = self.rt.num |
| 212 | 268 imm5 = self.imm5 |
| 219 | 269 |
| 270 h = (self.opcode << 11) | (imm5 << 6) | (Rn << 3) | Rt | |
| 271 return u16(h) | |
| 275 | 272 |
| 219 | 273 def __repr__(self): |
| 274 return '{} {}, {}'.format(self.mnemonic, self.rt, self.memloc) | |
| 275 | |
| 276 @armtarget.instruction | |
| 277 class storeimm5_ins(LS_imm5_base): | |
| 278 mnemonic = 'STR' | |
| 279 opcode = 0xC | |
| 280 | |
| 281 @armtarget.instruction | |
| 282 class loadimm5_ins(LS_imm5_base): | |
| 283 mnemonic = 'LDR' | |
| 284 opcode = 0xD | |
| 285 | |
| 286 class ls_sp_base_imm8(ArmInstruction): | |
| 224 | 287 operands = (Reg8Op, MemSpRel) |
| 219 | 288 def __init__(self, rt, memop): |
| 289 self.rt = rt | |
| 290 self.offset = memop.offset | |
| 291 | |
| 292 def encode(self): | |
| 293 rt = self.rt.num | |
| 294 assert rt < 8 | |
| 295 imm8 = self.offset >> 2 | |
| 296 assert imm8 < 256 | |
| 297 h = (self.opcode << 8) | (rt << 8) | imm8 | |
| 212 | 298 return u16(h) |
| 299 | |
| 219 | 300 def __repr__(self): |
| 301 return '{} {}, [sp,#{}]'.format(self.mnemonic, self.rt, self.offset) | |
| 302 | |
| 236 | 303 def align(x, m): |
| 304 while ((x % m) != 0): | |
| 305 x = x + 1 | |
| 306 return x | |
| 307 | |
| 212 | 308 @armtarget.instruction |
| 219 | 309 class ldr_pcrel(ArmInstruction): |
| 310 """ ldr Rt, [PC, imm8], store value into memory """ | |
| 212 | 311 mnemonic = 'ldr' |
| 235 | 312 operands = (RegOp, LabelRef) |
| 219 | 313 def __init__(self, rt, label): |
| 235 | 314 assert isinstance(label, LabelRef) |
| 219 | 315 self.rt = rt |
| 316 self.label = label | |
| 317 self.offset = 0 | |
| 212 | 318 |
| 234 | 319 def resolve(self, f): |
| 235 | 320 la = f(self.label.name) |
| 236 | 321 sa = align(self.address + 2, 4) |
| 322 self.offset = (la - sa) | |
| 235 | 323 if self.offset < 0: |
| 324 self.offset = 0 | |
| 234 | 325 |
| 212 | 326 def encode(self): |
| 219 | 327 rt = self.rt.num |
| 328 assert rt < 8 | |
| 329 imm8 = self.offset >> 2 | |
| 330 assert imm8 < 256 | |
| 235 | 331 assert imm8 >= 0 |
| 219 | 332 h = (0x9 << 11) | (rt << 8) | imm8 |
| 212 | 333 return u16(h) |
| 334 | |
| 219 | 335 def __repr__(self): |
| 232 | 336 return 'LDR {}, {}'.format(self.rt, self.label.name) |
| 219 | 337 |
| 338 @armtarget.instruction | |
| 339 class ldr_sprel(ls_sp_base_imm8): | |
| 340 """ ldr Rt, [SP, imm8] """ | |
| 341 mnemonic = 'LDR' | |
| 342 opcode = 0x98 | |
| 343 | |
| 344 @armtarget.instruction | |
| 345 class str_sprel(ls_sp_base_imm8): | |
| 346 """ str Rt, [SP, imm8] """ | |
| 347 mnemonic = 'STR' | |
| 348 opcode = 0x90 | |
| 349 | |
| 212 | 350 @armtarget.instruction |
| 202 | 351 class mov_ins(ArmInstruction): |
| 352 """ mov Rd, imm8, move immediate value into register """ | |
| 353 mnemonic = 'mov' | |
| 203 | 354 opcode = 4 # 00100 Rd(3) imm8 |
| 355 operands = (RegOp, Imm8) | |
| 356 def __init__(self, rd, imm): | |
| 357 self.imm = imm.imm | |
| 358 self.r = rd.num | |
| 205 | 359 |
| 202 | 360 def encode(self): |
| 361 rd = self.r | |
| 362 opcode = self.opcode | |
| 363 imm8 = self.imm | |
| 364 h = (opcode << 11) | (rd << 8) | imm8 | |
| 365 return u16(h) | |
| 219 | 366 def __repr__(self): |
| 367 return 'MOV {0}, xx?'.format(self.r) | |
| 232 | 368 |
| 369 | |
| 203 | 370 |
| 219 | 371 |
| 372 | |
| 373 # Arithmatics: | |
| 374 | |
| 275 | 375 |
| 376 | |
| 203 | 377 @armtarget.instruction |
| 378 class addregregimm3_ins(ArmInstruction): | |
| 379 """ add Rd, Rn, imm3 """ | |
| 380 mnemonic = 'add' | |
| 381 opcode = 3 # 00011 | |
| 382 operands = (RegOp, RegOp, Imm3) | |
| 205 | 383 irpattern = 3 |
| 203 | 384 def __init__(self, rd, rn, imm3): |
| 385 self.rd = rd | |
| 386 self.rn = rn | |
| 387 self.imm3 = imm3 | |
| 388 def encode(self): | |
| 389 rd = self.rd.num | |
| 390 rn = self.rn.num | |
| 391 imm3 = self.imm3.imm | |
| 392 opcode = self.opcode | |
| 393 h = (opcode << 11) | (1 << 10) | (imm3 << 6) | (rn << 3) | rd | |
| 394 return u16(h) | |
| 395 | |
| 219 | 396 class regregreg_base(ArmInstruction): |
| 397 """ ??? Rd, Rn, Rm """ | |
| 398 operands = (Reg8Op, Reg8Op, Reg8Op) | |
| 399 def __init__(self, rd, rn, rm): | |
| 400 self.rd = rd | |
| 401 self.rn = rn | |
| 402 self.rm = rm | |
| 403 def encode(self): | |
| 404 rd = self.rd.num | |
| 405 rn = self.rn.num | |
| 406 rm = self.rm.num | |
| 407 h = (self.opcode << 9) | (rm << 6) | (rn << 3) | rd | |
| 408 return u16(h) | |
| 409 def __repr__(self): | |
| 410 return '{} {}, {}, {}'.format(self.mnemonic, self.rd, self.rn, self.rm) | |
| 411 | |
| 412 @armtarget.instruction | |
| 413 class addregs_ins(regregreg_base): | |
| 414 mnemonic = 'ADD' | |
| 415 opcode = 0b0001100 | |
| 416 | |
| 417 @armtarget.instruction | |
| 418 class subregs_ins(regregreg_base): | |
| 419 mnemonic = 'SUB' | |
| 420 opcode = 0b0001101 | |
| 421 | |
| 275 | 422 |
| 423 @armtarget.instruction | |
| 424 class movregreg_ext_ins(ArmInstruction): | |
| 425 operands = (Reg16Op, Reg16Op) | |
| 426 mnemonic = 'MOV' | |
| 427 def __init__(self, rd, rm): | |
| 428 self.rd = rd | |
| 429 self.rm = rm | |
| 430 def encode(self): | |
| 431 Rd = self.rd.num & 0x7 | |
| 432 D = (self.rd.num >> 3) & 0x1 | |
| 433 Rm = self.rm.num | |
| 434 opcode = 0b01000110 | |
| 435 return u16((opcode << 8) | (D << 7) |(Rm << 3) | Rd) | |
| 436 def __repr__(self): | |
| 437 return '{} {}, {}'.format(self.mnemonic, self.rd, self.rm) | |
| 438 | |
| 439 | |
| 440 | |
| 219 | 441 class regreg_base(ArmInstruction): |
| 442 """ ??? Rdn, Rm """ | |
| 443 operands = (Reg8Op, Reg8Op) | |
| 444 def __init__(self, rdn, rm): | |
| 445 self.rdn = rdn | |
| 446 self.rm = rm | |
| 447 def encode(self): | |
| 448 rdn = self.rdn.num | |
| 449 rm = self.rm.num | |
| 450 h = (self.opcode << 6) | (rm << 3) | rdn | |
| 451 return u16(h) | |
| 452 def __repr__(self): | |
| 453 return '{} {}, {}'.format(self.mnemonic, self.rdn, self.rm) | |
| 454 | |
| 455 @armtarget.instruction | |
| 258 | 456 class movregreg_ins(regreg_base): |
| 457 """ mov Rd, Rm """ | |
| 458 mnemonic = 'mov' | |
| 459 opcode = 0 | |
| 460 | |
| 461 @armtarget.instruction | |
| 219 | 462 class andregs_ins(regreg_base): |
| 463 mnemonic = 'AND' | |
| 464 opcode = 0b0100000000 | |
| 465 | |
| 466 @armtarget.instruction | |
| 467 class orrregs_ins(regreg_base): | |
| 468 mnemonic = 'ORR' | |
| 469 opcode = 0b0100001100 | |
| 470 | |
| 471 @armtarget.instruction | |
| 472 class cmp_ins(regreg_base): | |
| 473 mnemonic = 'CMP' | |
| 474 opcode = 0b0100001010 | |
| 475 | |
| 203 | 476 @armtarget.instruction |
| 232 | 477 class lslregs_ins(regreg_base): |
| 478 mnemonic = 'LSL' | |
| 479 opcode = 0b0100000010 | |
| 480 | |
| 481 @armtarget.instruction | |
| 203 | 482 class cmpregimm8_ins(ArmInstruction): |
| 483 """ cmp Rn, imm8 """ | |
| 484 mnemonic = 'cmp' | |
| 485 opcode = 5 # 00101 | |
| 486 operands = (RegOp, Imm8) | |
| 487 def __init__(self, rn, imm): | |
| 488 self.rn = rn | |
| 489 self.imm = imm | |
| 490 def encode(self): | |
| 491 rn = self.rn.num | |
| 492 imm = self.imm.imm | |
| 493 opcode = self.opcode | |
| 494 h = (opcode << 11) | (rn << 8) | imm | |
| 495 return u16(h) | |
| 202 | 496 |
| 219 | 497 # Jumping: |
| 218 | 498 |
| 238 | 499 def wrap_negative(x, bits): |
| 500 b = struct.unpack('<I', struct.pack('<i', x))[0] | |
| 501 mask = (1 << bits) - 1 | |
| 502 return b & mask | |
| 503 | |
| 237 | 504 class jumpBase_ins(ArmInstruction): |
| 505 operands = (LabelRef,) | |
| 205 | 506 def __init__(self, target_label): |
| 237 | 507 assert type(target_label) is LabelRef |
| 205 | 508 self.target = target_label |
| 237 | 509 self.offset = 0 |
| 510 | |
| 511 def resolve(self, f): | |
| 512 la = f(self.target.name) | |
| 238 | 513 sa = self.address + 4 |
| 237 | 514 self.offset = (la - sa) |
| 238 | 515 #if self.offset < 0: |
| 516 # # TODO: handle negative jump | |
| 517 # self.offset = 0 | |
| 237 | 518 |
| 219 | 519 def __repr__(self): |
| 237 | 520 return '{} {}'.format(self.mnemonic, self.target.name) |
| 219 | 521 |
| 522 @armtarget.instruction | |
| 237 | 523 class b_ins(jumpBase_ins): |
| 524 mnemonic = 'B' | |
| 525 def encode(self): | |
| 238 | 526 imm11 = wrap_negative(self.offset >> 1, 11) |
| 527 h = (0b11100 << 11) | imm11 # | 1 # 1 to enable thumb mode | |
| 237 | 528 return u16(h) |
| 529 | |
|
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530 @armtarget.instruction |
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531 class bl_ins(jumpBase_ins): |
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532 mnemonic = 'BL' |
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533 def encode(self): |
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534 imm32 = wrap_negative(self.offset >> 1, 32) |
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535 imm11 = imm32 & 0x7FF |
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536 imm10 = (imm32 >> 11) & 0x3FF |
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537 j1 = 1 # TODO: what do these mean? |
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538 j2 = 1 |
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539 s = (imm32 >> 24) & 0x1 |
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540 h1 = (0b11110 << 11) | (s << 10) | imm10 |
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541 h2 = (0b1101 << 12) | (j1 << 13) | (j2 << 11) | imm11 |
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542 return u16(h1) + u16(h2) |
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543 |
| 237 | 544 class cond_base_ins(jumpBase_ins): |
| 545 def encode(self): | |
| 238 | 546 imm8 = wrap_negative(self.offset >> 1, 8) |
| 237 | 547 h = (0b1101 << 12) | (self.cond << 8) | imm8 |
| 548 return u16(h) | |
| 549 | |
| 262 | 550 |
| 237 | 551 @armtarget.instruction |
| 552 class beq_ins(cond_base_ins): | |
| 219 | 553 mnemonic = 'beq' |
| 237 | 554 cond = 0 |
| 555 | |
| 262 | 556 |
| 237 | 557 @armtarget.instruction |
| 262 | 558 class bne_ins(cond_base_ins): |
| 237 | 559 mnemonic = 'bne' |
| 560 cond = 1 | |
| 205 | 561 |
| 262 | 562 |
| 563 @armtarget.instruction | |
| 564 class blt_ins(cond_base_ins): | |
| 565 mnemonic = 'blt' | |
| 566 cond = 0b1011 | |
| 567 | |
| 568 | |
| 569 @armtarget.instruction | |
| 570 class blt_ins(cond_base_ins): | |
| 571 mnemonic = 'bgt' | |
| 572 cond = 0b1100 | |
| 573 | |
| 574 | |
| 205 | 575 @armtarget.instruction |
| 576 class push_ins(ArmInstruction): | |
| 206 | 577 operands = (RegisterSet,) |
| 205 | 578 mnemonic = 'push' |
| 579 def __init__(self, regs): | |
| 206 | 580 assert (type(regs),) == self.operands, (type(regs),) |
| 205 | 581 self.regs = regs |
| 206 | 582 def __repr__(self): |
| 583 return '{0} {{{1}}}'.format(self.mnemonic, self.regs) | |
| 205 | 584 def encode(self): |
| 206 | 585 reg_list = 0 |
| 586 M = 0 | |
| 587 for n in self.regs.registerNumbers(): | |
| 588 if n < 8: | |
| 589 reg_list |= (1 << n) | |
| 590 elif n == 14: | |
| 591 M = 1 | |
| 592 else: | |
| 593 raise NotImplementedError('not implemented for this register') | |
| 594 h = (0x5a << 9) | (M << 8) | reg_list | |
| 595 return u16(h) | |
| 205 | 596 |
| 597 @armtarget.instruction | |
| 598 class pop_ins(ArmInstruction): | |
| 206 | 599 operands = (RegisterSet,) |
| 205 | 600 mnemonic = 'pop' |
| 601 def __init__(self, regs): | |
| 602 self.regs = regs | |
| 207 | 603 def __repr__(self): |
| 604 return '{0} {{{1}}}'.format(self.mnemonic, self.regs) | |
| 205 | 605 def encode(self): |
| 206 | 606 reg_list = 0 |
| 607 P = 0 | |
| 608 for n in self.regs.registerNumbers(): | |
| 609 if n < 8: | |
| 610 reg_list |= (1 << n) | |
| 611 elif n == 15: | |
| 612 P = 1 | |
| 613 else: | |
| 614 raise NotImplementedError('not implemented for this register') | |
| 615 h = (0x5E << 9) | (P << 8) | reg_list | |
| 616 return u16(h) | |
| 205 | 617 |
| 618 @armtarget.instruction | |
| 202 | 619 class yield_ins(ArmInstruction): |
| 620 operands = () | |
| 621 mnemonic = 'yield' | |
| 622 def encode(self): | |
| 623 return u16(0xbf10) | |
| 624 | |
| 275 | 625 # misc: |
| 626 | |
| 627 # add/sub SP: | |
| 628 @armtarget.instruction | |
| 629 class addspsp_ins(ArmInstruction): | |
| 630 operands = (RegSpOp, RegSpOp, Imm7) | |
| 631 mnemonic = 'add' | |
| 632 def __init__(self, _sp, _sp2, imm7): | |
| 633 self.imm7 = imm7.imm | |
| 634 assert self.imm7 % 4 == 0 | |
| 635 self.imm7 >>= 2 | |
| 636 | |
| 637 def encode(self): | |
| 638 return u16((0b101100000 << 7) |self.imm7) | |
| 639 | |
| 640 @armtarget.instruction | |
| 641 class subspsp_ins(ArmInstruction): | |
| 642 operands = (RegSpOp, RegSpOp, Imm7) | |
| 643 mnemonic = 'sub' | |
| 644 def __init__(self, _sp, _sp2, imm7): | |
| 645 self.imm7 = imm7.imm | |
| 646 assert self.imm7 % 4 == 0 | |
| 647 self.imm7 >>= 2 | |
| 648 | |
| 649 def encode(self): | |
| 650 return u16((0b101100001 << 7) |self.imm7) | |
| 651 | |
| 206 | 652 armtarget.check() |
| 653 |