annotate python/cortexm3.py @ 279:2ccd57b1d78c

Fix register allocator to do burn2 OK
author Windel Bouwman
date Sat, 12 Oct 2013 09:56:23 +0200
parents 046017431c6a
children 02385f62f250
rev   line source
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1 import struct
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2 import types
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3 from target import Register, Instruction, Target, Imm8, Label, Imm3, LabelRef, Imm32, Imm7
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4 from asmnodes import ASymbol, ANumber, AUnop, ABinop
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5 from ppci import CompilerError
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6 import ir
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7
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8 # TODO: encode this in DSL (domain specific language)
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9 # TBD: is this required?
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10
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11 def u16(h):
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12 return struct.pack('<H', h)
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13
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14 def u32(x):
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15 return struct.pack('<I', x)
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16
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17 armtarget = Target('arm')
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18
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19 class ArmRegister(Register):
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20 def __init__(self, num, name):
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21 super().__init__(name)
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22 self.num = num
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23
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24 def __repr__(self):
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25 return self.name
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26
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27 @classmethod
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28 def Create(cls, vop):
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29 if type(vop) is ASymbol:
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30 name = vop.name
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31 regs = {}
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32 for r in armtarget.registers:
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33 regs[r.name] = r
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34 if name in regs:
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35 r = regs[name]
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36 if isinstance(r, cls):
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37 return r
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38
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39
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40 class Reg8Op(ArmRegister):
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41 pass
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42
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43
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44 class Reg16Op(ArmRegister):
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45 pass
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46
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47
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48 class RegSpOp:
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49 @classmethod
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50 def Create(cls, vop):
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51 if type(vop) is ASymbol:
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52 if vop.name.lower() == 'sp':
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53 return cls()
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54
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55 def getRegNum(n):
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56 for r in armtarget.registers:
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57 if r.num == n:
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58 return r
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59
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60 def getRegisterRange(n1, n2):
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61 regs = []
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62 if n1.num < n2.num:
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63 for n in range(n1.num, n2.num + 1):
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64 r = getRegNum(n)
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65 assert r
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66 regs.append(r)
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67 return regs
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68
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69 def isRegOffset(regname, x, y):
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70 if type(x) is ASymbol and type(y) is ANumber and x.name.upper() == regname:
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71 return y.number
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72 elif type(y) is ASymbol and type(x) is ANumber and y.name.upper() == regname:
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73 return x.number
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74
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75
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76 class MemRegXRel:
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77 def __init__(self, offset):
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78 assert offset % 4 == 0
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79 self.offset = offset
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80
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81 def __repr__(self):
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82 return '[{}, #{}]'.format(self.regname, self.offset)
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83
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84 @classmethod
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85 def Create(cls, vop):
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86 if type(vop) is AUnop and vop.operation == '[]' and type(vop.arg) is ABinop and vop.arg.op == '+':
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87 vop = vop.arg # descent
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88 offset = isRegOffset(cls.regname, vop.arg1, vop.arg2)
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89 if type(offset) is int:
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90 if offset % 4 == 0:
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91 offset = vop.arg2.number
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92 return cls(offset)
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93 elif type(vop) is ASymbol and vop.name.upper() == self.regname:
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94 return cls(0)
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95
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96
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97 class MemSpRel(MemRegXRel):
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98 regname = 'SP'
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99
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100
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101 class MemR8Rel:
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102 def __init__(self, basereg, offset):
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103 assert type(basereg) is Reg8Op
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104 self.basereg = basereg
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105 self.offset = offset
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106
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107 def __repr__(self):
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108 return '[{}, #{}]'.format(self.basereg, self.offset)
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109
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110 @classmethod
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111 def Create(cls, vop):
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112 if type(vop) is AUnop and vop.operation == '[]':
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113 vop = vop.arg # descent
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114 if type(vop) is ABinop:
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115 if vop.op == '+' and type(vop.arg1) is ASymbol and type(vop.arg2) is ANumber:
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116 offset = vop.arg2.number
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117 if offset > 120:
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118 return
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119 basereg = Reg8Op.Create(vop.arg1)
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120 if not basereg:
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121 return
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122 else:
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123 return
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124 elif type(vop) is ASymbol:
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125 offset = 0
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126 basereg = Reg8Op.Create(vop)
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127 if not basereg:
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128 return
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129 else:
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130 return
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131 return cls(getRegNum(basereg.num), offset)
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132
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133 class RegisterSet:
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134 def __init__(self, regs):
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135 assert type(regs) is set
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136 self.regs = regs
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137
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138 def __repr__(self):
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139 return ','.join([str(r) for r in self.regs])
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140
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141 @classmethod
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142 def Create(cls, vop):
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143 assert type(vop) is AUnop and vop.operation == '{}'
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144 assert type(vop.arg) is list
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145 regs = set()
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146 for arg in vop.arg:
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147 if type(arg) is ASymbol:
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148 reg = ArmRegister.Create(arg)
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149 if not reg:
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150 return
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151 regs.add(reg)
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152 elif type(arg) is ABinop and arg.op == '-':
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153 reg1 = ArmRegister.Create(arg.arg1)
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154 reg2 = ArmRegister.Create(arg.arg2)
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155 if not reg1:
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156 return
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157 if not reg2:
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158 return
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159 for r in getRegisterRange(reg1, reg2):
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160 regs.add(r)
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161 else:
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162 raise Exception('Cannot be')
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163 return cls(regs)
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164
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165 def registerNumbers(self):
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166 return [r.num for r in self.regs]
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167
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168 def makeReg(cls, num, name):
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169 r = cls(num, name)
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170 armtarget.registers.append(r)
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171 return r
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172
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173 # 8 bit registers:
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174 r0 = makeReg(Reg8Op, 0, 'r0')
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175 r1 = makeReg(Reg8Op, 1, 'r1')
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176 r2 = makeReg(Reg8Op, 2, 'r2')
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177 r3 = makeReg(Reg8Op, 3, 'r3')
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178 r4 = makeReg(Reg8Op, 4, 'r4')
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179 r5 = makeReg(Reg8Op, 5, 'r5')
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180 r6 = makeReg(Reg8Op, 6, 'r6')
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181 r7 = makeReg(Reg8Op, 7, 'r7')
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182 # Other registers:
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183 # TODO
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184 sp = makeReg(ArmRegister, 13, 'sp')
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185 lr = makeReg(ArmRegister, 14, 'lr')
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186 pc = makeReg(ArmRegister, 15, 'pc')
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187
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188 assert isinstance(sp, ArmRegister)
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189 assert isinstance(r3, ArmRegister)
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190 assert ArmRegister.Create(ASymbol('r3')) is r3
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191 assert ArmRegister.Create(ASymbol('sp')) is sp
276
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192
202
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193 class ArmInstruction(Instruction):
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194 pass
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195
235
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196
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197 @armtarget.instruction
205
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198 class dcd_ins(ArmInstruction):
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199 mnemonic = 'dcd'
235
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diff changeset
200 operands = (Imm32,)
205
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201 def __init__(self, expr):
237
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202 if isinstance(expr, Imm32):
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203 self.expr = expr.imm
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204 self.label = None
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205 elif isinstance(expr, LabelRef):
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diff changeset
206 self.expr = 0
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diff changeset
207 self.label = expr
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208 else:
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diff changeset
209 raise NotImplementedError()
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210
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diff changeset
211 def resolve(self, f):
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212 if self.label:
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diff changeset
213 self.expr = f(self.label.name)
219
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214
205
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215 def encode(self):
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216 return u32(self.expr)
202
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217
219
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diff changeset
218 def __repr__(self):
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219 return 'DCD 0x{0:X}'.format(self.expr)
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220
279
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221 @armtarget.instruction
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222 class nop_ins(ArmInstruction):
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223 mnemonic = 'nop'
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224 operands = tuple()
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225
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226 def encode(self):
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227 return bytes()
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228
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229 def __repr__(self):
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230 return 'NOP'
219
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231
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232
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233 # Memory related
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234
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235 class LS_imm5_base(ArmInstruction):
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236 """ ??? Rt, [Rn, imm5] """
225
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237 operands = (Reg8Op, MemR8Rel)
212
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238 def __init__(self, rt, memop):
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239 assert memop.offset % 4 == 0
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240 self.imm5 = memop.offset >> 2
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241 self.rn = memop.basereg.num
225
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242 self.rt = rt
219
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diff changeset
243 self.memloc = memop
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244 assert self.rn < 8
225
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diff changeset
245 assert self.rt.num < 8
212
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246
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diff changeset
247 def encode(self):
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248 Rn = self.rn
225
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diff changeset
249 Rt = self.rt.num
212
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diff changeset
250 imm5 = self.imm5
219
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251
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diff changeset
252 h = (self.opcode << 11) | (imm5 << 6) | (Rn << 3) | Rt
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253 return u16(h)
275
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254
219
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diff changeset
255 def __repr__(self):
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256 return '{} {}, {}'.format(self.mnemonic, self.rt, self.memloc)
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257
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diff changeset
258 @armtarget.instruction
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259 class storeimm5_ins(LS_imm5_base):
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260 mnemonic = 'STR'
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diff changeset
261 opcode = 0xC
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262
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diff changeset
263 @armtarget.instruction
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264 class loadimm5_ins(LS_imm5_base):
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265 mnemonic = 'LDR'
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diff changeset
266 opcode = 0xD
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267
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diff changeset
268 class ls_sp_base_imm8(ArmInstruction):
224
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diff changeset
269 operands = (Reg8Op, MemSpRel)
219
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diff changeset
270 def __init__(self, rt, memop):
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271 self.rt = rt
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272 self.offset = memop.offset
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273
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diff changeset
274 def encode(self):
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275 rt = self.rt.num
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276 assert rt < 8
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diff changeset
277 imm8 = self.offset >> 2
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278 assert imm8 < 256
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279 h = (self.opcode << 8) | (rt << 8) | imm8
212
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280 return u16(h)
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281
219
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diff changeset
282 def __repr__(self):
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283 return '{} {}, [sp,#{}]'.format(self.mnemonic, self.rt, self.offset)
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284
236
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diff changeset
285 def align(x, m):
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diff changeset
286 while ((x % m) != 0):
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diff changeset
287 x = x + 1
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diff changeset
288 return x
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289
277
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290
212
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diff changeset
291 @armtarget.instruction
219
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diff changeset
292 class ldr_pcrel(ArmInstruction):
276
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diff changeset
293 """ ldr Rt, LABEL, load value from pc relative position """
212
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diff changeset
294 mnemonic = 'ldr'
277
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diff changeset
295 operands = (Reg8Op, LabelRef)
219
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diff changeset
296 def __init__(self, rt, label):
235
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diff changeset
297 assert isinstance(label, LabelRef)
219
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diff changeset
298 self.rt = rt
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diff changeset
299 self.label = label
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diff changeset
300 self.offset = 0
212
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diff changeset
301
234
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diff changeset
302 def resolve(self, f):
235
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diff changeset
303 la = f(self.label.name)
236
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diff changeset
304 sa = align(self.address + 2, 4)
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diff changeset
305 self.offset = (la - sa)
235
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diff changeset
306 if self.offset < 0:
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diff changeset
307 self.offset = 0
234
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diff changeset
308
212
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diff changeset
309 def encode(self):
219
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diff changeset
310 rt = self.rt.num
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diff changeset
311 assert rt < 8
279
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diff changeset
312 assert self.offset % 4 == 0
219
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diff changeset
313 imm8 = self.offset >> 2
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diff changeset
314 assert imm8 < 256
235
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diff changeset
315 assert imm8 >= 0
219
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diff changeset
316 h = (0x9 << 11) | (rt << 8) | imm8
212
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diff changeset
317 return u16(h)
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diff changeset
318
219
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diff changeset
319 def __repr__(self):
232
e621e3ba78d2 Added left shift instruction
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diff changeset
320 return 'LDR {}, {}'.format(self.rt, self.label.name)
219
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diff changeset
321
277
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diff changeset
322
219
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diff changeset
323 @armtarget.instruction
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diff changeset
324 class ldr_sprel(ls_sp_base_imm8):
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diff changeset
325 """ ldr Rt, [SP, imm8] """
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diff changeset
326 mnemonic = 'LDR'
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diff changeset
327 opcode = 0x98
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diff changeset
328
277
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diff changeset
329
219
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diff changeset
330 @armtarget.instruction
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diff changeset
331 class str_sprel(ls_sp_base_imm8):
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diff changeset
332 """ str Rt, [SP, imm8] """
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diff changeset
333 mnemonic = 'STR'
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diff changeset
334 opcode = 0x90
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diff changeset
335
277
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diff changeset
336
212
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diff changeset
337 @armtarget.instruction
202
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338 class mov_ins(ArmInstruction):
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339 """ mov Rd, imm8, move immediate value into register """
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340 mnemonic = 'mov'
203
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diff changeset
341 opcode = 4 # 00100 Rd(3) imm8
277
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diff changeset
342 operands = (Reg8Op, Imm8)
203
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diff changeset
343 def __init__(self, rd, imm):
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diff changeset
344 self.imm = imm.imm
277
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diff changeset
345 self.rd = rd
205
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diff changeset
346
202
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347 def encode(self):
277
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diff changeset
348 rd = self.rd.num
202
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349 opcode = self.opcode
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350 imm8 = self.imm
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351 h = (opcode << 11) | (rd << 8) | imm8
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352 return u16(h)
277
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diff changeset
353
219
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diff changeset
354 def __repr__(self):
277
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diff changeset
355 return 'MOV {}, {}'.format(self.rd, self.imm)
203
ca1ea402f6a1 Added some arm instructions
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diff changeset
356
219
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diff changeset
357
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diff changeset
358
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diff changeset
359 # Arithmatics:
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diff changeset
360
275
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diff changeset
361
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diff changeset
362
276
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parents: 275
diff changeset
363 class regregimm3_base(ArmInstruction):
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diff changeset
364 operands = (Reg8Op, Reg8Op, Imm3)
203
ca1ea402f6a1 Added some arm instructions
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parents: 202
diff changeset
365 def __init__(self, rd, rn, imm3):
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diff changeset
366 self.rd = rd
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diff changeset
367 self.rn = rn
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diff changeset
368 self.imm3 = imm3
277
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diff changeset
369
203
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diff changeset
370 def encode(self):
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diff changeset
371 rd = self.rd.num
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diff changeset
372 rn = self.rn.num
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diff changeset
373 imm3 = self.imm3.imm
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diff changeset
374 opcode = self.opcode
276
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parents: 275
diff changeset
375 h = (self.opcode << 9) | (imm3 << 6) | (rn << 3) | rd
203
ca1ea402f6a1 Added some arm instructions
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diff changeset
376 return u16(h)
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diff changeset
377
277
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diff changeset
378 def __repr__(self):
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diff changeset
379 return '{} {}, {}, {}'.format(self.mnemonic, self.rd, self.rn, self.imm3.imm)
276
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parents: 275
diff changeset
380
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diff changeset
381 @armtarget.instruction
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parents: 275
diff changeset
382 class addregregimm3_ins(regregimm3_base):
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parents: 275
diff changeset
383 """ add Rd, Rn, imm3 """
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diff changeset
384 mnemonic = 'add'
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parents: 275
diff changeset
385 opcode = 0b0001110
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parents: 275
diff changeset
386
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parents: 275
diff changeset
387
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parents: 275
diff changeset
388 @armtarget.instruction
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parents: 275
diff changeset
389 class subregregimm3_ins(regregimm3_base):
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parents: 275
diff changeset
390 """ sub Rd, Rn, imm3 """
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parents: 275
diff changeset
391 mnemonic = 'sub'
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parents: 275
diff changeset
392 opcode = 0b0001111
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parents: 275
diff changeset
393
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parents: 275
diff changeset
394
219
1fa3e0050b49 Expanded ad hoc code generator
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parents: 218
diff changeset
395 class regregreg_base(ArmInstruction):
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parents: 218
diff changeset
396 """ ??? Rd, Rn, Rm """
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parents: 218
diff changeset
397 operands = (Reg8Op, Reg8Op, Reg8Op)
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parents: 218
diff changeset
398 def __init__(self, rd, rn, rm):
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parents: 218
diff changeset
399 self.rd = rd
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parents: 218
diff changeset
400 self.rn = rn
1fa3e0050b49 Expanded ad hoc code generator
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parents: 218
diff changeset
401 self.rm = rm
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parents: 218
diff changeset
402 def encode(self):
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parents: 218
diff changeset
403 rd = self.rd.num
1fa3e0050b49 Expanded ad hoc code generator
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parents: 218
diff changeset
404 rn = self.rn.num
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Windel Bouwman
parents: 218
diff changeset
405 rm = self.rm.num
1fa3e0050b49 Expanded ad hoc code generator
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parents: 218
diff changeset
406 h = (self.opcode << 9) | (rm << 6) | (rn << 3) | rd
1fa3e0050b49 Expanded ad hoc code generator
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parents: 218
diff changeset
407 return u16(h)
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Windel Bouwman
parents: 218
diff changeset
408 def __repr__(self):
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parents: 218
diff changeset
409 return '{} {}, {}, {}'.format(self.mnemonic, self.rd, self.rn, self.rm)
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parents: 218
diff changeset
410
277
046017431c6a Started register allocator
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parents: 276
diff changeset
411
219
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
412 @armtarget.instruction
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parents: 218
diff changeset
413 class addregs_ins(regregreg_base):
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parents: 218
diff changeset
414 mnemonic = 'ADD'
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parents: 218
diff changeset
415 opcode = 0b0001100
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Windel Bouwman
parents: 218
diff changeset
416
277
046017431c6a Started register allocator
Windel Bouwman
parents: 276
diff changeset
417
219
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
418 @armtarget.instruction
1fa3e0050b49 Expanded ad hoc code generator
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parents: 218
diff changeset
419 class subregs_ins(regregreg_base):
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parents: 218
diff changeset
420 mnemonic = 'SUB'
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parents: 218
diff changeset
421 opcode = 0b0001101
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Windel Bouwman
parents: 218
diff changeset
422
275
6f2423df0675 Fixed serve arm-as
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parents: 268
diff changeset
423
277
046017431c6a Started register allocator
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parents: 276
diff changeset
424
275
6f2423df0675 Fixed serve arm-as
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parents: 268
diff changeset
425 @armtarget.instruction
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diff changeset
426 class movregreg_ext_ins(ArmInstruction):
277
046017431c6a Started register allocator
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parents: 276
diff changeset
427 operands = (ArmRegister, ArmRegister)
275
6f2423df0675 Fixed serve arm-as
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parents: 268
diff changeset
428 mnemonic = 'MOV'
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parents: 268
diff changeset
429 def __init__(self, rd, rm):
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diff changeset
430 self.rd = rd
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diff changeset
431 self.rm = rm
277
046017431c6a Started register allocator
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parents: 276
diff changeset
432
275
6f2423df0675 Fixed serve arm-as
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diff changeset
433 def encode(self):
6f2423df0675 Fixed serve arm-as
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diff changeset
434 Rd = self.rd.num & 0x7
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diff changeset
435 D = (self.rd.num >> 3) & 0x1
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parents: 268
diff changeset
436 Rm = self.rm.num
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diff changeset
437 opcode = 0b01000110
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diff changeset
438 return u16((opcode << 8) | (D << 7) |(Rm << 3) | Rd)
277
046017431c6a Started register allocator
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parents: 276
diff changeset
439
275
6f2423df0675 Fixed serve arm-as
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parents: 268
diff changeset
440 def __repr__(self):
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parents: 268
diff changeset
441 return '{} {}, {}'.format(self.mnemonic, self.rd, self.rm)
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parents: 268
diff changeset
442
6f2423df0675 Fixed serve arm-as
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diff changeset
443
276
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parents: 275
diff changeset
444 @armtarget.instruction
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parents: 275
diff changeset
445 class mulregreg_ins(ArmInstruction):
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parents: 275
diff changeset
446 """ mul Rn, Rdm """
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parents: 275
diff changeset
447 operands = (Reg8Op, Reg8Op)
279
2ccd57b1d78c Fix register allocator to do burn2 OK
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parents: 277
diff changeset
448 mnemonic = 'MUL'
276
Windel Bouwman
parents: 275
diff changeset
449 def __init__(self, rn, rdm):
Windel Bouwman
parents: 275
diff changeset
450 self.rn = rn
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parents: 275
diff changeset
451 self.rdm = rdm
277
046017431c6a Started register allocator
Windel Bouwman
parents: 276
diff changeset
452
276
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parents: 275
diff changeset
453 def encode(self):
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parents: 275
diff changeset
454 rn = self.rn.num
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parents: 275
diff changeset
455 rdm = self.rdm.num
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parents: 275
diff changeset
456 opcode = 0b0100001101
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parents: 275
diff changeset
457 h = (opcode << 6) | (rn << 3) | rdm
Windel Bouwman
parents: 275
diff changeset
458 return u16(h)
277
046017431c6a Started register allocator
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parents: 276
diff changeset
459
276
Windel Bouwman
parents: 275
diff changeset
460 def __repr__(self):
277
046017431c6a Started register allocator
Windel Bouwman
parents: 276
diff changeset
461 return '{} {}, {}'.format(self.mnemonic, self.rn, self.rdm)
046017431c6a Started register allocator
Windel Bouwman
parents: 276
diff changeset
462
275
6f2423df0675 Fixed serve arm-as
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parents: 268
diff changeset
463
219
1fa3e0050b49 Expanded ad hoc code generator
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parents: 218
diff changeset
464 class regreg_base(ArmInstruction):
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Windel Bouwman
parents: 218
diff changeset
465 """ ??? Rdn, Rm """
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parents: 218
diff changeset
466 operands = (Reg8Op, Reg8Op)
277
046017431c6a Started register allocator
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parents: 276
diff changeset
467 # TODO: integrate with the code gen interface:
046017431c6a Started register allocator
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parents: 276
diff changeset
468 src = (0, 1)
046017431c6a Started register allocator
Windel Bouwman
parents: 276
diff changeset
469 dst = (0,)
219
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
470 def __init__(self, rdn, rm):
1fa3e0050b49 Expanded ad hoc code generator
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parents: 218
diff changeset
471 self.rdn = rdn
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
472 self.rm = rm
277
046017431c6a Started register allocator
Windel Bouwman
parents: 276
diff changeset
473
219
1fa3e0050b49 Expanded ad hoc code generator
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parents: 218
diff changeset
474 def encode(self):
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Windel Bouwman
parents: 218
diff changeset
475 rdn = self.rdn.num
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
476 rm = self.rm.num
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parents: 218
diff changeset
477 h = (self.opcode << 6) | (rm << 3) | rdn
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Windel Bouwman
parents: 218
diff changeset
478 return u16(h)
277
046017431c6a Started register allocator
Windel Bouwman
parents: 276
diff changeset
479
219
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
480 def __repr__(self):
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
481 return '{} {}, {}'.format(self.mnemonic, self.rdn, self.rm)
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
482
277
046017431c6a Started register allocator
Windel Bouwman
parents: 276
diff changeset
483
219
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
484 @armtarget.instruction
258
04c19282a5aa Added register allocator
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parents: 251
diff changeset
485 class movregreg_ins(regreg_base):
277
046017431c6a Started register allocator
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parents: 276
diff changeset
486 # TODO: match this:
046017431c6a Started register allocator
Windel Bouwman
parents: 276
diff changeset
487 pattern = ir.Move(ir.Temp, ir.Temp)
258
04c19282a5aa Added register allocator
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parents: 251
diff changeset
488 """ mov Rd, Rm """
04c19282a5aa Added register allocator
Windel Bouwman
parents: 251
diff changeset
489 mnemonic = 'mov'
04c19282a5aa Added register allocator
Windel Bouwman
parents: 251
diff changeset
490 opcode = 0
04c19282a5aa Added register allocator
Windel Bouwman
parents: 251
diff changeset
491
277
046017431c6a Started register allocator
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parents: 276
diff changeset
492
258
04c19282a5aa Added register allocator
Windel Bouwman
parents: 251
diff changeset
493 @armtarget.instruction
219
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
494 class andregs_ins(regreg_base):
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parents: 218
diff changeset
495 mnemonic = 'AND'
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parents: 218
diff changeset
496 opcode = 0b0100000000
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
497
277
046017431c6a Started register allocator
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parents: 276
diff changeset
498
219
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
499 @armtarget.instruction
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Windel Bouwman
parents: 218
diff changeset
500 class orrregs_ins(regreg_base):
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parents: 218
diff changeset
501 mnemonic = 'ORR'
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parents: 218
diff changeset
502 opcode = 0b0100001100
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
503
277
046017431c6a Started register allocator
Windel Bouwman
parents: 276
diff changeset
504
219
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
505 @armtarget.instruction
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
506 class cmp_ins(regreg_base):
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Windel Bouwman
parents: 218
diff changeset
507 mnemonic = 'CMP'
1fa3e0050b49 Expanded ad hoc code generator
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parents: 218
diff changeset
508 opcode = 0b0100001010
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
509
277
046017431c6a Started register allocator
Windel Bouwman
parents: 276
diff changeset
510
203
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
511 @armtarget.instruction
232
e621e3ba78d2 Added left shift instruction
Windel Bouwman
parents: 225
diff changeset
512 class lslregs_ins(regreg_base):
e621e3ba78d2 Added left shift instruction
Windel Bouwman
parents: 225
diff changeset
513 mnemonic = 'LSL'
e621e3ba78d2 Added left shift instruction
Windel Bouwman
parents: 225
diff changeset
514 opcode = 0b0100000010
e621e3ba78d2 Added left shift instruction
Windel Bouwman
parents: 225
diff changeset
515
e621e3ba78d2 Added left shift instruction
Windel Bouwman
parents: 225
diff changeset
516 @armtarget.instruction
203
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
517 class cmpregimm8_ins(ArmInstruction):
ca1ea402f6a1 Added some arm instructions
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parents: 202
diff changeset
518 """ cmp Rn, imm8 """
ca1ea402f6a1 Added some arm instructions
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parents: 202
diff changeset
519 mnemonic = 'cmp'
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
520 opcode = 5 # 00101
277
046017431c6a Started register allocator
Windel Bouwman
parents: 276
diff changeset
521 operands = (Reg8Op, Imm8)
203
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
522 def __init__(self, rn, imm):
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
523 self.rn = rn
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
524 self.imm = imm
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
525 def encode(self):
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
526 rn = self.rn.num
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
527 imm = self.imm.imm
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
528 opcode = self.opcode
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
529 h = (opcode << 11) | (rn << 8) | imm
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
530 return u16(h)
202
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
531
277
046017431c6a Started register allocator
Windel Bouwman
parents: 276
diff changeset
532
219
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
533 # Jumping:
218
494828a7adf1 added some sort of cache to assembler
Windel Bouwman
parents: 216
diff changeset
534
238
90637d1bbfad Added test sequence 2
Windel Bouwman
parents: 237
diff changeset
535 def wrap_negative(x, bits):
90637d1bbfad Added test sequence 2
Windel Bouwman
parents: 237
diff changeset
536 b = struct.unpack('<I', struct.pack('<i', x))[0]
90637d1bbfad Added test sequence 2
Windel Bouwman
parents: 237
diff changeset
537 mask = (1 << bits) - 1
90637d1bbfad Added test sequence 2
Windel Bouwman
parents: 237
diff changeset
538 return b & mask
90637d1bbfad Added test sequence 2
Windel Bouwman
parents: 237
diff changeset
539
237
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
540 class jumpBase_ins(ArmInstruction):
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
541 operands = (LabelRef,)
205
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
542 def __init__(self, target_label):
237
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
543 assert type(target_label) is LabelRef
205
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
544 self.target = target_label
237
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
545 self.offset = 0
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
546
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
547 def resolve(self, f):
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
548 la = f(self.target.name)
238
90637d1bbfad Added test sequence 2
Windel Bouwman
parents: 237
diff changeset
549 sa = self.address + 4
237
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
550 self.offset = (la - sa)
238
90637d1bbfad Added test sequence 2
Windel Bouwman
parents: 237
diff changeset
551 #if self.offset < 0:
90637d1bbfad Added test sequence 2
Windel Bouwman
parents: 237
diff changeset
552 # # TODO: handle negative jump
90637d1bbfad Added test sequence 2
Windel Bouwman
parents: 237
diff changeset
553 # self.offset = 0
237
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
554
219
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
555 def __repr__(self):
237
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
556 return '{} {}'.format(self.mnemonic, self.target.name)
219
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
557
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
558 @armtarget.instruction
237
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
559 class b_ins(jumpBase_ins):
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
560 mnemonic = 'B'
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
561 def encode(self):
238
90637d1bbfad Added test sequence 2
Windel Bouwman
parents: 237
diff changeset
562 imm11 = wrap_negative(self.offset >> 1, 11)
90637d1bbfad Added test sequence 2
Windel Bouwman
parents: 237
diff changeset
563 h = (0b11100 << 11) | imm11 # | 1 # 1 to enable thumb mode
237
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
564 return u16(h)
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
565
251
6ed3d3a82a63 Added another c3 example. First import attempt
Windel Bouwman
parents: 238
diff changeset
566 @armtarget.instruction
6ed3d3a82a63 Added another c3 example. First import attempt
Windel Bouwman
parents: 238
diff changeset
567 class bl_ins(jumpBase_ins):
6ed3d3a82a63 Added another c3 example. First import attempt
Windel Bouwman
parents: 238
diff changeset
568 mnemonic = 'BL'
6ed3d3a82a63 Added another c3 example. First import attempt
Windel Bouwman
parents: 238
diff changeset
569 def encode(self):
6ed3d3a82a63 Added another c3 example. First import attempt
Windel Bouwman
parents: 238
diff changeset
570 imm32 = wrap_negative(self.offset >> 1, 32)
6ed3d3a82a63 Added another c3 example. First import attempt
Windel Bouwman
parents: 238
diff changeset
571 imm11 = imm32 & 0x7FF
6ed3d3a82a63 Added another c3 example. First import attempt
Windel Bouwman
parents: 238
diff changeset
572 imm10 = (imm32 >> 11) & 0x3FF
6ed3d3a82a63 Added another c3 example. First import attempt
Windel Bouwman
parents: 238
diff changeset
573 j1 = 1 # TODO: what do these mean?
6ed3d3a82a63 Added another c3 example. First import attempt
Windel Bouwman
parents: 238
diff changeset
574 j2 = 1
6ed3d3a82a63 Added another c3 example. First import attempt
Windel Bouwman
parents: 238
diff changeset
575 s = (imm32 >> 24) & 0x1
6ed3d3a82a63 Added another c3 example. First import attempt
Windel Bouwman
parents: 238
diff changeset
576 h1 = (0b11110 << 11) | (s << 10) | imm10
6ed3d3a82a63 Added another c3 example. First import attempt
Windel Bouwman
parents: 238
diff changeset
577 h2 = (0b1101 << 12) | (j1 << 13) | (j2 << 11) | imm11
6ed3d3a82a63 Added another c3 example. First import attempt
Windel Bouwman
parents: 238
diff changeset
578 return u16(h1) + u16(h2)
6ed3d3a82a63 Added another c3 example. First import attempt
Windel Bouwman
parents: 238
diff changeset
579
237
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
580 class cond_base_ins(jumpBase_ins):
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581 def encode(self):
238
90637d1bbfad Added test sequence 2
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582 imm8 = wrap_negative(self.offset >> 1, 8)
237
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583 h = (0b1101 << 12) | (self.cond << 8) | imm8
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584 return u16(h)
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585
262
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586
237
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587 @armtarget.instruction
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588 class beq_ins(cond_base_ins):
219
1fa3e0050b49 Expanded ad hoc code generator
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589 mnemonic = 'beq'
237
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590 cond = 0
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parents: 236
diff changeset
591
262
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592
237
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parents: 236
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593 @armtarget.instruction
262
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594 class bne_ins(cond_base_ins):
237
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595 mnemonic = 'bne'
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parents: 236
diff changeset
596 cond = 1
205
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parents: 203
diff changeset
597
262
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parents: 261
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598
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parents: 261
diff changeset
599 @armtarget.instruction
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600 class blt_ins(cond_base_ins):
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601 mnemonic = 'blt'
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602 cond = 0b1011
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parents: 261
diff changeset
603
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parents: 261
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604
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parents: 261
diff changeset
605 @armtarget.instruction
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606 class blt_ins(cond_base_ins):
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607 mnemonic = 'bgt'
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608 cond = 0b1100
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609
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parents: 261
diff changeset
610
205
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parents: 203
diff changeset
611 @armtarget.instruction
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612 class push_ins(ArmInstruction):
206
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613 operands = (RegisterSet,)
205
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614 mnemonic = 'push'
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615 def __init__(self, regs):
206
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616 assert (type(regs),) == self.operands, (type(regs),)
205
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617 self.regs = regs
206
6c6bf8890d8a Added push and pop encodings
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618 def __repr__(self):
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619 return '{0} {{{1}}}'.format(self.mnemonic, self.regs)
205
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620 def encode(self):
206
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diff changeset
621 reg_list = 0
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622 M = 0
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623 for n in self.regs.registerNumbers():
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624 if n < 8:
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diff changeset
625 reg_list |= (1 << n)
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diff changeset
626 elif n == 14:
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627 M = 1
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diff changeset
628 else:
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diff changeset
629 raise NotImplementedError('not implemented for this register')
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630 h = (0x5a << 9) | (M << 8) | reg_list
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631 return u16(h)
205
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632
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633 @armtarget.instruction
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634 class pop_ins(ArmInstruction):
206
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635 operands = (RegisterSet,)
205
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636 mnemonic = 'pop'
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637 def __init__(self, regs):
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638 self.regs = regs
207
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639 def __repr__(self):
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parents: 206
diff changeset
640 return '{0} {{{1}}}'.format(self.mnemonic, self.regs)
205
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diff changeset
641 def encode(self):
206
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parents: 205
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642 reg_list = 0
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643 P = 0
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parents: 205
diff changeset
644 for n in self.regs.registerNumbers():
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645 if n < 8:
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parents: 205
diff changeset
646 reg_list |= (1 << n)
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parents: 205
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647 elif n == 15:
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parents: 205
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648 P = 1
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parents: 205
diff changeset
649 else:
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parents: 205
diff changeset
650 raise NotImplementedError('not implemented for this register')
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parents: 205
diff changeset
651 h = (0x5E << 9) | (P << 8) | reg_list
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parents: 205
diff changeset
652 return u16(h)
205
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parents: 203
diff changeset
653
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parents: 203
diff changeset
654 @armtarget.instruction
202
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parents:
diff changeset
655 class yield_ins(ArmInstruction):
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parents:
diff changeset
656 operands = ()
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parents:
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657 mnemonic = 'yield'
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parents:
diff changeset
658 def encode(self):
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parents:
diff changeset
659 return u16(0xbf10)
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parents:
diff changeset
660
275
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diff changeset
661 # misc:
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662
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diff changeset
663 # add/sub SP:
277
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diff changeset
664 class addspsp_base(ArmInstruction):
275
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665 operands = (RegSpOp, RegSpOp, Imm7)
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diff changeset
666 def __init__(self, _sp, _sp2, imm7):
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667 self.imm7 = imm7.imm
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diff changeset
668 assert self.imm7 % 4 == 0
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diff changeset
669 self.imm7 >>= 2
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parents: 268
diff changeset
670
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parents: 268
diff changeset
671 def encode(self):
277
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parents: 276
diff changeset
672 return u16((self.opcode << 7) |self.imm7)
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parents: 276
diff changeset
673
046017431c6a Started register allocator
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parents: 276
diff changeset
674 def __repr__(self):
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parents: 276
diff changeset
675 return '{} sp, sp, {}'.format(self.mnemonic, self.imm7 << 2)
275
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parents: 268
diff changeset
676
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parents: 268
diff changeset
677 @armtarget.instruction
277
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diff changeset
678 class addspsp_ins(addspsp_base):
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diff changeset
679 mnemonic = 'add'
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parents: 276
diff changeset
680 opcode = 0b101100000
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diff changeset
681
046017431c6a Started register allocator
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parents: 276
diff changeset
682
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parents: 276
diff changeset
683 @armtarget.instruction
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diff changeset
684 class subspsp_ins(addspsp_base):
275
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diff changeset
685 mnemonic = 'sub'
277
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parents: 276
diff changeset
686 opcode = 0b101100001
275
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parents: 268
diff changeset
687
206
6c6bf8890d8a Added push and pop encodings
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parents: 205
diff changeset
688 armtarget.check()
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Windel Bouwman
parents: 205
diff changeset
689