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342
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1
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364
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2 from ..basetarget import Instruction, LabelAddress
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365
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3 from ...bitfun import encode_imm32
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342
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4
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5 from .token import ArmToken
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345
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6 from .registers import R0, SP, ArmRegister
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7
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8
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342
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9
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10 # Instructions:
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11
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12 class ArmInstruction(Instruction):
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13 def __init__(self):
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14 self.token = ArmToken()
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15
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16
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353
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17 class ConstantData(ArmInstruction):
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346
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18 def __init__(self, v):
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19 super().__init__()
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353
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20 assert isinstance(v, int)
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346
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21 self.v = v
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22
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353
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23
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364
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24 class Dcd(ArmInstruction):
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25 def __init__(self, v):
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26 super().__init__()
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27 assert isinstance(v, int) or isinstance(v, LabelAddress)
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28 self.v = v
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29
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346
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30 def encode(self):
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364
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31 if type(self.v) is int:
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32 self.token[0:32] = self.v
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33 else:
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34 self.token[0:32] = 0
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346
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35 return self.token.encode()
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36
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364
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37 def relocations(self):
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38 if type(self.v) is LabelAddress:
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39 return [(self.v.name, 'absaddr32')]
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40 return []
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41
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350
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42 def __repr__(self):
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364
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43 if type(self.v) is int:
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44 return 'DCD {}'.format(hex(self.v))
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45 else:
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46 return 'DCD ={}'.format(self.v.name)
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350
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47
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346
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48
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353
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49 class Db(ConstantData):
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50 def encode(self):
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51 assert self.v < 256
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52 return bytes([self.v])
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53
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54 def __repr__(self):
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55 return 'DB {}'.format(hex(self.v))
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56
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57
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346
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58 def Mov(*args):
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59 if len(args) == 2:
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60 if isinstance(args[1], int):
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61 return Mov1(*args)
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62 elif isinstance(args[1], ArmRegister):
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63 return Mov2(*args)
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64 raise Exception()
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65
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66
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67 class Mov1(ArmInstruction):
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342
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68 """ Mov Rd, imm16 """
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69 def __init__(self, reg, imm):
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70 super().__init__()
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346
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71 assert type(imm) is int
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342
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72 self.reg = reg
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73 self.imm = imm
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74
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75 def encode(self):
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346
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76 self.token[0:12] = encode_imm32(self.imm)
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345
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77 self.token.Rd = self.reg.num
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342
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78 self.token[16:20] = 0
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346
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79 self.token[20] = 0 # Set flags
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342
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80 self.token[21:28] = 0b0011101
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346
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81 self.token.cond = AL
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342
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82 return self.token.encode()
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83
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84 def __repr__(self):
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345
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85 return 'Mov {}, {}'.format(self.reg, self.imm)
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86
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87
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346
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88 class Mov2(ArmInstruction):
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89 def __init__(self, rd, rm):
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90 super().__init__()
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91 self.rd = rd
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92 self.rm = rm
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93
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94 def encode(self):
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95 self.token[0:4] = self.rm.num
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96 self.token[4:12] = 0
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97 self.token[12:16] = self.rd.num
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98 self.token[16:20] = 0
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99 self.token.S = 0
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100 self.token[21:28] = 0xD
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101 self.token.cond = AL
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102 return self.token.encode()
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103
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350
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104 def __repr__(self):
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105 return 'MOV {}, {}'.format(self.rd, self.rm)
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106
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346
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107
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352
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108 def Cmp(*args):
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109 if len(args) == 2:
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110 if isinstance(args[1], int):
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111 return Cmp1(*args)
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112 elif isinstance(args[1], ArmRegister):
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113 return Cmp2(*args)
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114 raise Exception()
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115
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116
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117 class Cmp1(ArmInstruction):
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118 """ CMP Rn, imm """
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119 def __init__(self, reg, imm):
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120 super().__init__()
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121 assert type(imm) is int
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122 self.reg = reg
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123 self.imm = imm
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124
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125 def encode(self):
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126 self.token[0:12] = encode_imm32(self.imm)
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127 self.token.Rn = self.reg.num
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128 self.token[20:28] = 0b00110101
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129 self.token.cond = AL
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130 return self.token.encode()
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131
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132 def __repr__(self):
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133 return 'CMP {}, {}'.format(self.reg, self.imm)
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134
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135
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136 class Cmp2(ArmInstruction):
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137 """ CMP Rn, Rm """
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138 def __init__(self, rn, rm):
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139 super().__init__()
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140 self.rn = rn
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141 self.rm = rm
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142
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143 def encode(self):
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144 self.token.Rn = self.rn.num
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145 self.token.Rm = self.rm.num
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146 self.token[7:16] = 0
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147 self.token[20:28] = 0b10101
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148 self.token.cond = AL
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149 return self.token.encode()
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150
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151 def __repr__(self):
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152 return 'CMP {}, {}'.format(self.rn, self.rm)
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153
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154
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345
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155 def Add(*args):
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156 if len(args) == 3 and isinstance(args[0], ArmRegister) and \
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157 isinstance(args[1], ArmRegister):
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158 if isinstance(args[2], ArmRegister):
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159 return Add1(args[0], args[1], args[2])
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160 elif isinstance(args[2], int):
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161 return Add2(args[0], args[1], args[2])
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162 raise Exception()
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163
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164 def Sub(*args):
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165 if len(args) == 3 and isinstance(args[0], ArmRegister) and \
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166 isinstance(args[1], ArmRegister):
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167 if isinstance(args[2], ArmRegister):
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168 return Sub1(args[0], args[1], args[2])
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169 elif isinstance(args[2], int):
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170 return Sub2(args[0], args[1], args[2])
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171 raise Exception()
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172
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352
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173
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346
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174 def Mul(*args):
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175 return Mul1(args[0], args[1], args[2])
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176
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177
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354
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178 class Mul1(ArmInstruction):
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346
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179 def __init__(self, rd, rn, rm):
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180 super().__init__()
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181 self.rd = rd
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182 self.rn = rn
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183 self.rm = rm
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184
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185 def encode(self):
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186 self.token[0:4] = self.rn.num
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187 self.token[4:8] = 0b1001
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188 self.token[8:12] = self.rm.num
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189 self.token[16:20] = self.rd.num
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190 self.token.S = 0
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191 self.token.cond = AL
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192 return self.token.encode()
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193
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194
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345
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195 class OpRegRegReg(ArmInstruction):
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196 """ add rd, rn, rm """
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197 def __init__(self, rd, rn, rm, shift=0):
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198 super().__init__()
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199 self.rd = rd
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200 self.rn = rn
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201 self.rm = rm
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202
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203 def encode(self):
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204 self.token[0:4] = self.rm.num
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205 self.token[4] = 0
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206 self.token[5:7] = 0
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207 self.token[7:12] = 0 # Shift
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208 self.token.Rd = self.rd.num
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209 self.token.Rn = self.rn.num
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210 self.token.S = 0 # Set flags
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211 self.token[21:28] = self.opcode
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212 self.token.cond = 0xE # Always!
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213 return self.token.encode()
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214
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215 def __repr__(self):
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354
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216 return '{} {}, {}, {}'.format(self.mnemonic, self.rd, self.rn, self.rm)
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345
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217
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218
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219 class Add1(OpRegRegReg):
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354
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220 mnemonic = 'ADD'
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345
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221 opcode = 0b0000100
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222
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223
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224 class Sub1(OpRegRegReg):
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354
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225 mnemonic = 'SUB'
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345
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226 opcode = 0b0000010
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227
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228
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229 class Orr1(OpRegRegReg):
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354
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230 mnemonic = 'ORR'
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345
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231 opcode = 0b0001100
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232
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342
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233
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356
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234 class And1(OpRegRegReg):
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235 mnemonic = 'AND'
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236 opcode = 0b0000000
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237
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238
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239 class ShiftBase(ArmInstruction):
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240 """ ? rd, rn, rm """
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241 def __init__(self, rd, rn, rm):
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242 super().__init__()
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243 self.rd = rd
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244 self.rn = rn
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245 self.rm = rm
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246
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247 def encode(self):
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248 self.token[0:4] = self.rn.num
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249 self.token[4:8] = self.opcode
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250 self.token[8:12] = self.rm.num
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251 self.token[12:16] = self.rd.num
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252 self.token.S = 0 # Set flags
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253 self.token[21:28] = 0b1101
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254 self.token.cond = 0xE # Always!
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255 return self.token.encode()
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256
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257 def __repr__(self):
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258 return '{} {}, {}, {}'.format(self.mnemonic, self.rd, self.rn, self.rm)
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259
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260
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261 class Lsr1(ShiftBase):
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262 mnemonic = 'LSR'
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263 opcode = 0b0011
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264
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265
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266 class Lsl1(ShiftBase):
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267 mnemonic = 'LSL'
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268 opcode = 0b0001
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269
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270
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345
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271 class OpRegRegImm(ArmInstruction):
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272 """ add rd, rn, imm12 """
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273 def __init__(self, rd, rn, imm):
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274 super().__init__()
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275 self.rd = rd
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276 self.rn = rn
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277 self.imm2 = encode_imm32(imm)
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278 self.imm = imm
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279
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280 def encode(self):
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281 self.token[0:12] = self.imm2
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282 self.token.Rd = self.rd.num
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283 self.token.Rn = self.rn.num
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284 self.token.S = 0 # Set flags
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285 self.token[21:28] = self.opcode
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286 self.token.cond = 0xE # Always!
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287 return self.token.encode()
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288
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289 def __repr__(self):
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354
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290 return '{} {}, {}, {}'.format(self.mnemonic, self.rd, self.rn, self.imm)
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345
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291
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292
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293 class Add2(OpRegRegImm):
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354
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294 mnemonic = 'ADD'
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345
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295 opcode = 0b0010100
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296
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297
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298 class Sub2(OpRegRegImm):
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354
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299 mnemonic = 'SUB'
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345
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300 opcode = 0b0010010
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301
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302
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303
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304 # Branches:
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305
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306 class BranchBaseRoot(ArmInstruction):
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307 def __init__(self, target):
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308 super().__init__()
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309 self.target = target
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310
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311 def encode(self):
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312 self.token.cond = self.cond
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313 self.token[24:28] = self.opcode
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314 return self.token.encode()
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315
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316 def relocations(self):
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317 return [(self.target, 'b_imm24')]
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318
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350
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319 def __repr__(self):
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320 mnemonic = self.__class__.__name__
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321 return '{} {}'.format(mnemonic, self.target)
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322
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345
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323
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346
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324 EQ, NE, CS, CC, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL = range(15)
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325
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345
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326 class BranchBase(BranchBaseRoot):
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327 opcode = 0b1010
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328
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329 class BranchLinkBase(BranchBaseRoot):
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330 opcode = 0b1011
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331
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332 class Bl(BranchLinkBase):
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346
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333 cond = AL
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345
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334
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335 class B(BranchBase):
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346
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336 cond = AL
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345
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337
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338 class Beq(BranchBase):
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346
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339 cond = EQ
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345
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340
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341 class Bgt(BranchBase):
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346
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342 cond = GT
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345
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343
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360
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344 class Bge(BranchBase):
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345 cond = GE
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346
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345
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347 class Ble(BranchBase):
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346
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348 cond = LE
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349
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350 class Blt(BranchBase):
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351 cond = LT
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352
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352
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353 class Bne(BranchBase):
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354 cond = NE
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346
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355
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356 # Memory:
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357
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358 def reg_list_to_mask(reg_list):
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359 mask = 0
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360 for reg in reg_list:
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361 mask |= (1 << reg.num)
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362 return mask
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363
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364
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365 class Push(ArmInstruction):
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366 def __init__(self, register_set):
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367 super().__init__()
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368 self.reg_list = register_set
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369
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370 def encode(self):
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371 self.token.cond = AL
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372 self.token[16:28] = 0b100100101101
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373 reg_list = 0
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374 self.token[0:16] = reg_list_to_mask(self.reg_list)
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375 return self.token.encode()
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376
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350
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377 def __repr__(self):
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378 return 'PUSH {}'.format(self.reg_list)
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379
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380
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346
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381 class Pop(ArmInstruction):
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382 def __init__(self, register_set):
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383 super().__init__()
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384 self.reg_list = register_set
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385
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386 def encode(self):
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387 self.token.cond = AL
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388 self.token[16:28] = 0b100010111101
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389 self.token[0:16] = reg_list_to_mask(self.reg_list)
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390 return self.token.encode()
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345
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391
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350
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392 def __repr__(self):
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393 return 'POP {}'.format(self.reg_list)
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394
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345
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395
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346
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396 def Ldr(*args):
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350
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397 """ Convenience function that creates the correct instruction """
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398 if len(args) == 3:
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399 if isinstance(args[1], ArmRegister):
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400 return Ldr1(*args)
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401 elif len(args) == 2:
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402 if isinstance(args[1], ArmRegister):
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403 return Ldr1(args[0], args[1], 0)
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404 elif isinstance(args[1], str):
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405 return Ldr3(*args)
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346
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406 raise Exception()
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407
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350
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408
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375
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409 def LdrPseudo(rt, lab):
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410 """ Ldr rt, =lab ==> ldr rt, [pc, offset in litpool] ... dcd lab """
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411 return Ldr(rt, R0)
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412
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346
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413 def Str(*args):
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414 if len(args) == 3 and isinstance(args[1], ArmRegister):
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415 return Str1(*args)
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416 elif len(args) == 2 and isinstance(args[1], ArmRegister):
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417 return Str1(args[0], args[1], 0)
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418 raise Exception()
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419
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420
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421 class LdrStrBase(ArmInstruction):
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422 def __init__(self, rt, rn, offset):
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423 super().__init__()
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424 self.rt = rt
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425 self.rn = rn
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426 self.offset = offset
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427
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428 def encode(self):
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429 self.token.cond = AL
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430 self.token.Rn = self.rn.num
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431 self.token[25:28] = self.opcode
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432 self.token[20] = self.bit20
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433 self.token[12:16] = self.rt.num
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434 self.token[24] = 1 # Index
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435 if self.offset >= 0:
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436 self.token[23] = 1 # U == 1 'add'
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437 self.token[0:12] = self.offset
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438 else:
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439 self.token[23] = 0
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440 self.token[0:12] = -self.offset
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441 return self.token.encode()
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442
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350
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443 def __repr__(self):
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444 return '{} {}, [{}, {}]'.format(self.mnemonic, self.rt, self.rn,
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445 hex(self.offset))
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346
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446
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354
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447
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346
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448 class Str1(LdrStrBase):
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449 opcode = 0b010
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450 bit20 = 0
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350
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451 mnemonic = 'STR'
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346
|
452
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453
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454 class Ldr1(LdrStrBase):
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455 opcode = 0b010
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456 bit20 = 1
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350
|
457 mnemonic = 'LDR'
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|
346
|
458
|
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459
|
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354
|
460 class Adr(ArmInstruction):
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461 def __init__(self, rd, label):
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462 super().__init__()
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463 self.rd = rd
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464 self.label = label
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465
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466 def __repr__(self):
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467 return 'ADR {}, {}'.format(self.rd, self.label)
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468
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|
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469 def relocations(self):
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470 return [(self.label, 'adr_imm12')]
|
|
|
471
|
|
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472 def encode(self):
|
|
|
473 self.token.cond = AL
|
|
|
474 self.token[0:12] = 0 # Filled by linker
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|
|
475 self.token[12:16] = self.rd.num
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|
|
476 self.token[16:20] = 0b1111
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|
|
477 self.token[25] = 1
|
|
|
478 return self.token.encode()
|
|
|
479
|
|
|
480
|
|
346
|
481 class Ldr3(ArmInstruction):
|
|
350
|
482 """ Load PC relative constant value
|
|
|
483 LDR rt, label
|
|
|
484 encoding A1
|
|
|
485 """
|
|
346
|
486 def __init__(self, rt, label):
|
|
350
|
487 super().__init__()
|
|
346
|
488 self.rt = rt
|
|
|
489 self.label = label
|
|
|
490
|
|
350
|
491 def __repr__(self):
|
|
|
492 return 'LDR {}, {}'.format(self.rt, self.label)
|
|
|
493
|
|
|
494 def relocations(self):
|
|
|
495 return [(self.label, 'ldr_imm12')]
|
|
|
496
|
|
|
497 def encode(self):
|
|
|
498 self.token.cond = AL
|
|
|
499 self.token[0:12] = 0 # Filled by linker
|
|
|
500 self.token[12:16] = self.rt.num
|
|
|
501 self.token[16:23] = 0b0011111
|
|
|
502 self.token[24:28] = 0b0101
|
|
|
503 return self.token.encode()
|
|
362
|
504
|
|
|
505
|
|
|
506 class McrBase(ArmInstruction):
|
|
|
507 """ Mov arm register to coprocessor register """
|
|
|
508 def __init__(self, coproc, opc1, rt, crn, crm, opc2):
|
|
|
509 super().__init__()
|
|
|
510 self.coproc = coproc
|
|
|
511 self.opc1 = opc1
|
|
|
512 self.rt = rt
|
|
|
513 self.crn = crn
|
|
|
514 self.crm = crm
|
|
|
515 self.opc2 = opc2
|
|
|
516
|
|
|
517 def encode(self):
|
|
|
518 self.token[0:4] = self.crm
|
|
|
519 self.token[4] = 1
|
|
|
520 self.token[5:8] = self.opc2
|
|
|
521 self.token[8:12] = self.coproc
|
|
|
522 self.token[12:16] = self.rt.num
|
|
|
523 self.token[16:20] = self.crn
|
|
|
524 self.token[20] = self.b20
|
|
|
525 self.token[21:24] = self.opc1
|
|
|
526 self.token[24:28] = 0b1110
|
|
|
527 self.token.cond = AL
|
|
|
528 return self.token.encode()
|
|
|
529
|
|
|
530
|
|
|
531 class Mcr(McrBase):
|
|
|
532 b20 = 0
|
|
|
533
|
|
|
534
|
|
|
535 class Mrc(McrBase):
|
|
|
536 b20 = 1
|
