342
|
1
|
|
2 from ..basetarget import Instruction
|
346
|
3 from ...bitfun import rotate_left
|
342
|
4
|
|
5 from .token import ArmToken
|
345
|
6 from .registers import R0, SP, ArmRegister
|
|
7
|
|
8
|
|
9 def encode_imm32(v):
|
|
10 """ Bundle 32 bit value into 4 bits rotation and 8 bits value
|
|
11 """
|
|
12 for i in range(0, 16):
|
|
13 v2 = rotate_left(v, i*2)
|
|
14 if (v2 & 0xFFFFFF00) == 0:
|
|
15 rotation = i
|
|
16 val = v2 & 0xFF
|
|
17 x = (rotation << 8) | val
|
|
18 return x
|
|
19 raise Exception("Invalid value {}".format(v))
|
342
|
20
|
|
21 # Instructions:
|
|
22
|
|
23 class ArmInstruction(Instruction):
|
|
24 def __init__(self):
|
|
25 self.token = ArmToken()
|
|
26
|
|
27
|
346
|
28 class Dcd(ArmInstruction):
|
|
29 def __init__(self, v):
|
|
30 super().__init__()
|
|
31 self.v = v
|
|
32
|
|
33 def encode(self):
|
|
34 self.token[0:32] = self.v
|
|
35 return self.token.encode()
|
|
36
|
350
|
37 def __repr__(self):
|
|
38 return 'DCD {}'.format(hex(self.v))
|
|
39
|
346
|
40
|
|
41 def Mov(*args):
|
|
42 if len(args) == 2:
|
|
43 if isinstance(args[1], int):
|
|
44 return Mov1(*args)
|
|
45 elif isinstance(args[1], ArmRegister):
|
|
46 return Mov2(*args)
|
|
47 raise Exception()
|
|
48
|
|
49
|
|
50 class Mov1(ArmInstruction):
|
342
|
51 """ Mov Rd, imm16 """
|
|
52 def __init__(self, reg, imm):
|
|
53 super().__init__()
|
346
|
54 assert type(imm) is int
|
342
|
55 self.reg = reg
|
|
56 self.imm = imm
|
|
57
|
|
58 def encode(self):
|
346
|
59 self.token[0:12] = encode_imm32(self.imm)
|
345
|
60 self.token.Rd = self.reg.num
|
342
|
61 self.token[16:20] = 0
|
346
|
62 self.token[20] = 0 # Set flags
|
342
|
63 self.token[21:28] = 0b0011101
|
346
|
64 self.token.cond = AL
|
342
|
65 return self.token.encode()
|
|
66
|
|
67 def relocations(self):
|
|
68 return []
|
|
69
|
|
70 def __repr__(self):
|
345
|
71 return 'Mov {}, {}'.format(self.reg, self.imm)
|
|
72
|
|
73
|
346
|
74 class Mov2(ArmInstruction):
|
|
75 def __init__(self, rd, rm):
|
|
76 super().__init__()
|
|
77 self.rd = rd
|
|
78 self.rm = rm
|
|
79
|
|
80 def encode(self):
|
|
81 self.token[0:4] = self.rm.num
|
|
82 self.token[4:12] = 0
|
|
83 self.token[12:16] = self.rd.num
|
|
84 self.token[16:20] = 0
|
|
85 self.token.S = 0
|
|
86 self.token[21:28] = 0xD
|
|
87 self.token.cond = AL
|
|
88 return self.token.encode()
|
|
89
|
350
|
90 def __repr__(self):
|
|
91 return 'MOV {}, {}'.format(self.rd, self.rm)
|
|
92
|
346
|
93
|
345
|
94 def Add(*args):
|
|
95 if len(args) == 3 and isinstance(args[0], ArmRegister) and \
|
|
96 isinstance(args[1], ArmRegister):
|
|
97 if isinstance(args[2], ArmRegister):
|
|
98 return Add1(args[0], args[1], args[2])
|
|
99 elif isinstance(args[2], int):
|
|
100 return Add2(args[0], args[1], args[2])
|
|
101 raise Exception()
|
|
102
|
|
103 def Sub(*args):
|
|
104 if len(args) == 3 and isinstance(args[0], ArmRegister) and \
|
|
105 isinstance(args[1], ArmRegister):
|
|
106 if isinstance(args[2], ArmRegister):
|
|
107 return Sub1(args[0], args[1], args[2])
|
|
108 elif isinstance(args[2], int):
|
|
109 return Sub2(args[0], args[1], args[2])
|
|
110 raise Exception()
|
|
111
|
346
|
112 def Mul(*args):
|
|
113 return Mul1(args[0], args[1], args[2])
|
|
114
|
|
115
|
|
116 class Mul(ArmInstruction):
|
|
117 def __init__(self, rd, rn, rm):
|
|
118 super().__init__()
|
|
119 self.rd = rd
|
|
120 self.rn = rn
|
|
121 self.rm = rm
|
|
122
|
|
123 def encode(self):
|
|
124 self.token[0:4] = self.rn.num
|
|
125 self.token[4:8] = 0b1001
|
|
126 self.token[8:12] = self.rm.num
|
|
127 self.token[16:20] = self.rd.num
|
|
128 self.token.S = 0
|
|
129 self.token.cond = AL
|
|
130 return self.token.encode()
|
|
131
|
|
132
|
345
|
133 class OpRegRegReg(ArmInstruction):
|
|
134 """ add rd, rn, rm """
|
|
135 def __init__(self, rd, rn, rm, shift=0):
|
|
136 super().__init__()
|
|
137 self.rd = rd
|
|
138 self.rn = rn
|
|
139 self.rm = rm
|
|
140
|
|
141 def encode(self):
|
|
142 self.token[0:4] = self.rm.num
|
|
143 self.token[4] = 0
|
|
144 self.token[5:7] = 0
|
|
145 self.token[7:12] = 0 # Shift
|
|
146 self.token.Rd = self.rd.num
|
|
147 self.token.Rn = self.rn.num
|
|
148 self.token.S = 0 # Set flags
|
|
149 self.token[21:28] = self.opcode
|
|
150 self.token.cond = 0xE # Always!
|
|
151 return self.token.encode()
|
|
152
|
|
153 def __repr__(self):
|
|
154 return 'add {}, {}, {}'.format(self.rd, self.rn, self.rm)
|
|
155
|
|
156
|
|
157 class Add1(OpRegRegReg):
|
|
158 opcode = 0b0000100
|
|
159
|
|
160
|
|
161 class Sub1(OpRegRegReg):
|
|
162 opcode = 0b0000010
|
|
163
|
|
164
|
|
165 class Orr1(OpRegRegReg):
|
|
166 opcode = 0b0001100
|
|
167
|
342
|
168
|
345
|
169 class OpRegRegImm(ArmInstruction):
|
|
170 """ add rd, rn, imm12 """
|
|
171 def __init__(self, rd, rn, imm):
|
|
172 super().__init__()
|
|
173 self.rd = rd
|
|
174 self.rn = rn
|
|
175 self.imm2 = encode_imm32(imm)
|
|
176 self.imm = imm
|
|
177
|
|
178 def encode(self):
|
|
179 self.token[0:12] = self.imm2
|
|
180 self.token.Rd = self.rd.num
|
|
181 self.token.Rn = self.rn.num
|
|
182 self.token.S = 0 # Set flags
|
|
183 self.token[21:28] = self.opcode
|
|
184 self.token.cond = 0xE # Always!
|
|
185 return self.token.encode()
|
|
186
|
|
187 def __repr__(self):
|
|
188 return 'add {}, {}, {}'.format(self.rd, self.rn, self.imm)
|
|
189
|
|
190
|
|
191 class Add2(OpRegRegImm):
|
|
192 opcode = 0b0010100
|
|
193
|
|
194
|
|
195 class Sub2(OpRegRegImm):
|
|
196 opcode = 0b0010010
|
|
197
|
|
198
|
|
199
|
|
200 # Branches:
|
|
201
|
|
202 class BranchBaseRoot(ArmInstruction):
|
|
203 def __init__(self, target):
|
|
204 super().__init__()
|
|
205 self.target = target
|
|
206
|
|
207 def encode(self):
|
|
208 self.token.cond = self.cond
|
|
209 self.token[24:28] = self.opcode
|
|
210 return self.token.encode()
|
|
211
|
|
212 def relocations(self):
|
|
213 return [(self.target, 'b_imm24')]
|
|
214
|
350
|
215 def __repr__(self):
|
|
216 mnemonic = self.__class__.__name__
|
|
217 return '{} {}'.format(mnemonic, self.target)
|
|
218
|
345
|
219
|
346
|
220 EQ, NE, CS, CC, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL = range(15)
|
|
221
|
345
|
222 class BranchBase(BranchBaseRoot):
|
|
223 opcode = 0b1010
|
|
224
|
|
225 class BranchLinkBase(BranchBaseRoot):
|
|
226 opcode = 0b1011
|
|
227
|
|
228 class Bl(BranchLinkBase):
|
346
|
229 cond = AL
|
345
|
230
|
|
231 class B(BranchBase):
|
346
|
232 cond = AL
|
345
|
233
|
|
234 class Beq(BranchBase):
|
346
|
235 cond = EQ
|
345
|
236
|
|
237 class Bgt(BranchBase):
|
346
|
238 cond = GT
|
345
|
239
|
|
240 class Ble(BranchBase):
|
346
|
241 cond = LE
|
|
242
|
|
243 class Blt(BranchBase):
|
|
244 cond = LT
|
|
245
|
|
246
|
|
247 # Memory:
|
|
248
|
|
249 def reg_list_to_mask(reg_list):
|
|
250 mask = 0
|
|
251 for reg in reg_list:
|
|
252 mask |= (1 << reg.num)
|
|
253 return mask
|
|
254
|
|
255
|
|
256 class Push(ArmInstruction):
|
|
257 def __init__(self, register_set):
|
|
258 super().__init__()
|
|
259 self.reg_list = register_set
|
|
260
|
|
261 def encode(self):
|
|
262 self.token.cond = AL
|
|
263 self.token[16:28] = 0b100100101101
|
|
264 reg_list = 0
|
|
265 self.token[0:16] = reg_list_to_mask(self.reg_list)
|
|
266 return self.token.encode()
|
|
267
|
350
|
268 def __repr__(self):
|
|
269 return 'PUSH {}'.format(self.reg_list)
|
|
270
|
|
271
|
346
|
272 class Pop(ArmInstruction):
|
|
273 def __init__(self, register_set):
|
|
274 super().__init__()
|
|
275 self.reg_list = register_set
|
|
276
|
|
277 def encode(self):
|
|
278 self.token.cond = AL
|
|
279 self.token[16:28] = 0b100010111101
|
|
280 self.token[0:16] = reg_list_to_mask(self.reg_list)
|
|
281 return self.token.encode()
|
345
|
282
|
350
|
283 def __repr__(self):
|
|
284 return 'POP {}'.format(self.reg_list)
|
|
285
|
345
|
286
|
346
|
287 def Ldr(*args):
|
350
|
288 """ Convenience function that creates the correct instruction """
|
|
289 if len(args) == 3:
|
|
290 if isinstance(args[1], ArmRegister):
|
|
291 return Ldr1(*args)
|
|
292 elif len(args) == 2:
|
|
293 if isinstance(args[1], ArmRegister):
|
|
294 return Ldr1(args[0], args[1], 0)
|
|
295 elif isinstance(args[1], str):
|
|
296 return Ldr3(*args)
|
346
|
297 raise Exception()
|
|
298
|
350
|
299
|
346
|
300 def Str(*args):
|
|
301 if len(args) == 3 and isinstance(args[1], ArmRegister):
|
|
302 return Str1(*args)
|
|
303 elif len(args) == 2 and isinstance(args[1], ArmRegister):
|
|
304 return Str1(args[0], args[1], 0)
|
|
305 raise Exception()
|
|
306
|
|
307
|
|
308 class LdrStrBase(ArmInstruction):
|
|
309 def __init__(self, rt, rn, offset):
|
|
310 super().__init__()
|
|
311 self.rt = rt
|
|
312 self.rn = rn
|
|
313 self.offset = offset
|
|
314
|
|
315 def encode(self):
|
|
316 self.token.cond = AL
|
|
317 self.token.Rn = self.rn.num
|
|
318 self.token[25:28] = self.opcode
|
|
319 self.token[20] = self.bit20
|
|
320 self.token[12:16] = self.rt.num
|
|
321 self.token[24] = 1 # Index
|
|
322 if self.offset >= 0:
|
|
323 self.token[23] = 1 # U == 1 'add'
|
|
324 self.token[0:12] = self.offset
|
|
325 else:
|
|
326 self.token[23] = 0
|
|
327 self.token[0:12] = -self.offset
|
|
328 return self.token.encode()
|
|
329
|
350
|
330 def __repr__(self):
|
|
331 return '{} {}, [{}, {}]'.format(self.mnemonic, self.rt, self.rn,
|
|
332 hex(self.offset))
|
346
|
333
|
|
334 class Str1(LdrStrBase):
|
|
335 opcode = 0b010
|
|
336 bit20 = 0
|
350
|
337 mnemonic = 'STR'
|
346
|
338
|
|
339
|
|
340 class Ldr1(LdrStrBase):
|
|
341 opcode = 0b010
|
|
342 bit20 = 1
|
350
|
343 mnemonic = 'LDR'
|
346
|
344
|
|
345
|
|
346 class Ldr3(ArmInstruction):
|
350
|
347 """ Load PC relative constant value
|
|
348 LDR rt, label
|
|
349 encoding A1
|
|
350 """
|
346
|
351 def __init__(self, rt, label):
|
350
|
352 super().__init__()
|
346
|
353 self.rt = rt
|
|
354 self.label = label
|
|
355
|
350
|
356 def __repr__(self):
|
|
357 return 'LDR {}, {}'.format(self.rt, self.label)
|
|
358
|
|
359 def relocations(self):
|
|
360 return [(self.label, 'ldr_imm12')]
|
|
361
|
|
362 def encode(self):
|
|
363 self.token.cond = AL
|
|
364 self.token[0:12] = 0 # Filled by linker
|
|
365 self.token[12:16] = self.rt.num
|
|
366 self.token[16:23] = 0b0011111
|
|
367 self.token[24:28] = 0b0101
|
|
368 return self.token.encode()
|