--- a/python/ppci/target/arm/instructions.py	Fri Mar 14 10:30:13 2014 +0100
+++ b/python/ppci/target/arm/instructions.py	Fri Mar 14 13:02:16 2014 +0100
@@ -229,6 +229,43 @@
     opcode = 0b0001100
 
 
+class And1(OpRegRegReg):
+    mnemonic = 'AND'
+    opcode = 0b0000000
+
+
+class ShiftBase(ArmInstruction):
+    """ ? rd, rn, rm """
+    def __init__(self, rd, rn, rm):
+        super().__init__()
+        self.rd = rd
+        self.rn = rn
+        self.rm = rm
+
+    def encode(self):
+        self.token[0:4] = self.rn.num
+        self.token[4:8] = self.opcode
+        self.token[8:12] = self.rm.num
+        self.token[12:16] = self.rd.num
+        self.token.S = 0 # Set flags
+        self.token[21:28] = 0b1101
+        self.token.cond = 0xE # Always!
+        return self.token.encode()
+
+    def __repr__(self):
+        return '{} {}, {}, {}'.format(self.mnemonic, self.rd, self.rn, self.rm)
+
+
+class Lsr1(ShiftBase):
+    mnemonic = 'LSR'
+    opcode = 0b0011
+
+
+class Lsl1(ShiftBase):
+    mnemonic = 'LSL'
+    opcode = 0b0001
+
+
 class OpRegRegImm(ArmInstruction):
     """ add rd, rn, imm12 """
     def __init__(self, rd, rn, imm):