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342
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1
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2 from ..basetarget import Instruction
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346
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3 from ...bitfun import rotate_left
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342
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4
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5 from .token import ArmToken
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345
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6 from .registers import R0, SP, ArmRegister
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7
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8
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9 def encode_imm32(v):
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10 """ Bundle 32 bit value into 4 bits rotation and 8 bits value
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11 """
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12 for i in range(0, 16):
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13 v2 = rotate_left(v, i*2)
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14 if (v2 & 0xFFFFFF00) == 0:
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15 rotation = i
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16 val = v2 & 0xFF
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17 x = (rotation << 8) | val
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18 return x
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19 raise Exception("Invalid value {}".format(v))
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342
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20
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21 # Instructions:
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22
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23 class ArmInstruction(Instruction):
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24 def __init__(self):
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25 self.token = ArmToken()
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26
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27
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346
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28 class Dcd(ArmInstruction):
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29 def __init__(self, v):
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30 super().__init__()
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31 self.v = v
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32
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33 def encode(self):
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34 self.token[0:32] = self.v
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35 return self.token.encode()
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36
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350
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37 def __repr__(self):
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38 return 'DCD {}'.format(hex(self.v))
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39
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346
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40
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41 def Mov(*args):
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42 if len(args) == 2:
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43 if isinstance(args[1], int):
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44 return Mov1(*args)
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45 elif isinstance(args[1], ArmRegister):
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46 return Mov2(*args)
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47 raise Exception()
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48
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49
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50 class Mov1(ArmInstruction):
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342
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51 """ Mov Rd, imm16 """
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52 def __init__(self, reg, imm):
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53 super().__init__()
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346
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54 assert type(imm) is int
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342
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55 self.reg = reg
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56 self.imm = imm
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57
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58 def encode(self):
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346
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59 self.token[0:12] = encode_imm32(self.imm)
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345
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60 self.token.Rd = self.reg.num
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342
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61 self.token[16:20] = 0
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346
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62 self.token[20] = 0 # Set flags
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342
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63 self.token[21:28] = 0b0011101
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346
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64 self.token.cond = AL
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342
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65 return self.token.encode()
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66
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67 def __repr__(self):
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345
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68 return 'Mov {}, {}'.format(self.reg, self.imm)
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69
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70
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346
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71 class Mov2(ArmInstruction):
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72 def __init__(self, rd, rm):
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73 super().__init__()
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74 self.rd = rd
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75 self.rm = rm
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76
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77 def encode(self):
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78 self.token[0:4] = self.rm.num
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79 self.token[4:12] = 0
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80 self.token[12:16] = self.rd.num
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81 self.token[16:20] = 0
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82 self.token.S = 0
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83 self.token[21:28] = 0xD
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84 self.token.cond = AL
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85 return self.token.encode()
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86
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350
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87 def __repr__(self):
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88 return 'MOV {}, {}'.format(self.rd, self.rm)
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89
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346
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90
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352
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91 def Cmp(*args):
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92 if len(args) == 2:
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93 if isinstance(args[1], int):
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94 return Cmp1(*args)
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95 elif isinstance(args[1], ArmRegister):
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96 return Cmp2(*args)
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97 raise Exception()
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98
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99
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100 class Cmp1(ArmInstruction):
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101 """ CMP Rn, imm """
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102 def __init__(self, reg, imm):
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103 super().__init__()
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104 assert type(imm) is int
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105 self.reg = reg
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106 self.imm = imm
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107
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108 def encode(self):
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109 self.token[0:12] = encode_imm32(self.imm)
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110 self.token.Rn = self.reg.num
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111 self.token[20:28] = 0b00110101
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112 self.token.cond = AL
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113 return self.token.encode()
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114
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115 def __repr__(self):
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116 return 'CMP {}, {}'.format(self.reg, self.imm)
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117
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118
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119 class Cmp2(ArmInstruction):
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120 """ CMP Rn, Rm """
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121 def __init__(self, rn, rm):
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122 super().__init__()
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123 self.rn = rn
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124 self.rm = rm
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125
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126 def encode(self):
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127 self.token.Rn = self.rn.num
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128 self.token.Rm = self.rm.num
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129 self.token[7:16] = 0
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130 self.token[20:28] = 0b10101
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131 self.token.cond = AL
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132 return self.token.encode()
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133
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134 def __repr__(self):
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135 return 'CMP {}, {}'.format(self.rn, self.rm)
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136
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137
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345
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138 def Add(*args):
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139 if len(args) == 3 and isinstance(args[0], ArmRegister) and \
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140 isinstance(args[1], ArmRegister):
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141 if isinstance(args[2], ArmRegister):
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142 return Add1(args[0], args[1], args[2])
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143 elif isinstance(args[2], int):
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144 return Add2(args[0], args[1], args[2])
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145 raise Exception()
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146
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147 def Sub(*args):
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148 if len(args) == 3 and isinstance(args[0], ArmRegister) and \
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149 isinstance(args[1], ArmRegister):
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150 if isinstance(args[2], ArmRegister):
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151 return Sub1(args[0], args[1], args[2])
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152 elif isinstance(args[2], int):
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153 return Sub2(args[0], args[1], args[2])
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154 raise Exception()
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155
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352
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156
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346
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157 def Mul(*args):
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158 return Mul1(args[0], args[1], args[2])
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159
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160
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161 class Mul(ArmInstruction):
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162 def __init__(self, rd, rn, rm):
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163 super().__init__()
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164 self.rd = rd
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165 self.rn = rn
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166 self.rm = rm
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167
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168 def encode(self):
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169 self.token[0:4] = self.rn.num
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170 self.token[4:8] = 0b1001
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171 self.token[8:12] = self.rm.num
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172 self.token[16:20] = self.rd.num
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173 self.token.S = 0
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174 self.token.cond = AL
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175 return self.token.encode()
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176
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177
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345
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178 class OpRegRegReg(ArmInstruction):
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179 """ add rd, rn, rm """
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180 def __init__(self, rd, rn, rm, shift=0):
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181 super().__init__()
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182 self.rd = rd
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183 self.rn = rn
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184 self.rm = rm
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185
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186 def encode(self):
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187 self.token[0:4] = self.rm.num
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188 self.token[4] = 0
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189 self.token[5:7] = 0
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190 self.token[7:12] = 0 # Shift
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191 self.token.Rd = self.rd.num
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192 self.token.Rn = self.rn.num
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193 self.token.S = 0 # Set flags
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194 self.token[21:28] = self.opcode
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195 self.token.cond = 0xE # Always!
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196 return self.token.encode()
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197
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198 def __repr__(self):
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199 return 'add {}, {}, {}'.format(self.rd, self.rn, self.rm)
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200
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201
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202 class Add1(OpRegRegReg):
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203 opcode = 0b0000100
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204
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205
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206 class Sub1(OpRegRegReg):
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207 opcode = 0b0000010
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208
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209
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210 class Orr1(OpRegRegReg):
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211 opcode = 0b0001100
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212
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342
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213
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345
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214 class OpRegRegImm(ArmInstruction):
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215 """ add rd, rn, imm12 """
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216 def __init__(self, rd, rn, imm):
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217 super().__init__()
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218 self.rd = rd
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219 self.rn = rn
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220 self.imm2 = encode_imm32(imm)
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221 self.imm = imm
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222
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223 def encode(self):
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224 self.token[0:12] = self.imm2
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225 self.token.Rd = self.rd.num
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226 self.token.Rn = self.rn.num
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227 self.token.S = 0 # Set flags
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228 self.token[21:28] = self.opcode
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229 self.token.cond = 0xE # Always!
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230 return self.token.encode()
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231
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232 def __repr__(self):
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233 return 'add {}, {}, {}'.format(self.rd, self.rn, self.imm)
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234
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235
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236 class Add2(OpRegRegImm):
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237 opcode = 0b0010100
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238
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239
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240 class Sub2(OpRegRegImm):
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241 opcode = 0b0010010
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242
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243
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244
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245 # Branches:
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246
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247 class BranchBaseRoot(ArmInstruction):
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248 def __init__(self, target):
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249 super().__init__()
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250 self.target = target
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251
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252 def encode(self):
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253 self.token.cond = self.cond
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254 self.token[24:28] = self.opcode
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255 return self.token.encode()
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256
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257 def relocations(self):
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258 return [(self.target, 'b_imm24')]
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259
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350
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260 def __repr__(self):
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261 mnemonic = self.__class__.__name__
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262 return '{} {}'.format(mnemonic, self.target)
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263
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345
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264
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346
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265 EQ, NE, CS, CC, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL = range(15)
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266
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345
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267 class BranchBase(BranchBaseRoot):
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268 opcode = 0b1010
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269
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270 class BranchLinkBase(BranchBaseRoot):
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271 opcode = 0b1011
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272
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273 class Bl(BranchLinkBase):
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346
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274 cond = AL
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345
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275
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276 class B(BranchBase):
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346
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277 cond = AL
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278
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279 class Beq(BranchBase):
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346
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280 cond = EQ
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281
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282 class Bgt(BranchBase):
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283 cond = GT
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284
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285 class Ble(BranchBase):
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346
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286 cond = LE
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287
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288 class Blt(BranchBase):
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289 cond = LT
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290
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352
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291 class Bne(BranchBase):
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292 cond = NE
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346
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293
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294 # Memory:
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295
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296 def reg_list_to_mask(reg_list):
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297 mask = 0
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298 for reg in reg_list:
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299 mask |= (1 << reg.num)
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300 return mask
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301
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302
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303 class Push(ArmInstruction):
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304 def __init__(self, register_set):
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305 super().__init__()
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306 self.reg_list = register_set
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307
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308 def encode(self):
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309 self.token.cond = AL
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310 self.token[16:28] = 0b100100101101
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311 reg_list = 0
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312 self.token[0:16] = reg_list_to_mask(self.reg_list)
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313 return self.token.encode()
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314
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350
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315 def __repr__(self):
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316 return 'PUSH {}'.format(self.reg_list)
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317
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318
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346
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319 class Pop(ArmInstruction):
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320 def __init__(self, register_set):
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321 super().__init__()
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322 self.reg_list = register_set
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323
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324 def encode(self):
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325 self.token.cond = AL
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326 self.token[16:28] = 0b100010111101
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327 self.token[0:16] = reg_list_to_mask(self.reg_list)
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328 return self.token.encode()
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345
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329
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350
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330 def __repr__(self):
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331 return 'POP {}'.format(self.reg_list)
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332
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345
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333
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346
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334 def Ldr(*args):
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350
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335 """ Convenience function that creates the correct instruction """
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336 if len(args) == 3:
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337 if isinstance(args[1], ArmRegister):
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338 return Ldr1(*args)
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339 elif len(args) == 2:
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340 if isinstance(args[1], ArmRegister):
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341 return Ldr1(args[0], args[1], 0)
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342 elif isinstance(args[1], str):
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343 return Ldr3(*args)
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346
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344 raise Exception()
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345
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350
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346
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346
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347 def Str(*args):
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348 if len(args) == 3 and isinstance(args[1], ArmRegister):
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349 return Str1(*args)
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350 elif len(args) == 2 and isinstance(args[1], ArmRegister):
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351 return Str1(args[0], args[1], 0)
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352 raise Exception()
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353
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354
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355 class LdrStrBase(ArmInstruction):
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356 def __init__(self, rt, rn, offset):
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357 super().__init__()
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358 self.rt = rt
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359 self.rn = rn
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360 self.offset = offset
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361
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362 def encode(self):
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363 self.token.cond = AL
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364 self.token.Rn = self.rn.num
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365 self.token[25:28] = self.opcode
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366 self.token[20] = self.bit20
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367 self.token[12:16] = self.rt.num
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368 self.token[24] = 1 # Index
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369 if self.offset >= 0:
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370 self.token[23] = 1 # U == 1 'add'
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371 self.token[0:12] = self.offset
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372 else:
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373 self.token[23] = 0
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374 self.token[0:12] = -self.offset
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375 return self.token.encode()
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376
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350
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377 def __repr__(self):
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378 return '{} {}, [{}, {}]'.format(self.mnemonic, self.rt, self.rn,
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379 hex(self.offset))
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346
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380
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381 class Str1(LdrStrBase):
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382 opcode = 0b010
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383 bit20 = 0
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350
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384 mnemonic = 'STR'
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346
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385
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386
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387 class Ldr1(LdrStrBase):
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388 opcode = 0b010
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389 bit20 = 1
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350
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390 mnemonic = 'LDR'
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346
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391
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392
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393 class Ldr3(ArmInstruction):
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350
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394 """ Load PC relative constant value
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395 LDR rt, label
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396 encoding A1
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397 """
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346
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398 def __init__(self, rt, label):
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350
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399 super().__init__()
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346
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400 self.rt = rt
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401 self.label = label
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402
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350
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403 def __repr__(self):
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404 return 'LDR {}, {}'.format(self.rt, self.label)
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405
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406 def relocations(self):
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407 return [(self.label, 'ldr_imm12')]
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408
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409 def encode(self):
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410 self.token.cond = AL
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411 self.token[0:12] = 0 # Filled by linker
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412 self.token[12:16] = self.rt.num
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413 self.token[16:23] = 0b0011111
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414 self.token[24:28] = 0b0101
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415 return self.token.encode()
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