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342
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1
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2 from ..basetarget import Instruction
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346
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3 from ...bitfun import rotate_left
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342
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4
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5 from .token import ArmToken
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345
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6 from .registers import R0, SP, ArmRegister
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7
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8
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9 def encode_imm32(v):
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10 """ Bundle 32 bit value into 4 bits rotation and 8 bits value
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11 """
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12 for i in range(0, 16):
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13 v2 = rotate_left(v, i*2)
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14 if (v2 & 0xFFFFFF00) == 0:
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15 rotation = i
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16 val = v2 & 0xFF
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17 x = (rotation << 8) | val
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18 return x
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19 raise Exception("Invalid value {}".format(v))
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342
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20
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21 # Instructions:
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22
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23 class ArmInstruction(Instruction):
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24 def __init__(self):
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25 self.token = ArmToken()
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26
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27
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353
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28 class ConstantData(ArmInstruction):
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346
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29 def __init__(self, v):
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30 super().__init__()
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353
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31 assert isinstance(v, int)
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346
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32 self.v = v
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33
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353
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34 def __repr__(self):
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35 return 'DCD {}'.format(hex(self.v))
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36
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37
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38 class Dcd(ConstantData):
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346
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39 def encode(self):
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40 self.token[0:32] = self.v
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41 return self.token.encode()
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42
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350
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43 def __repr__(self):
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44 return 'DCD {}'.format(hex(self.v))
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45
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346
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46
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353
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47 class Db(ConstantData):
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48 def encode(self):
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49 assert self.v < 256
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50 return bytes([self.v])
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51
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52 def __repr__(self):
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53 return 'DB {}'.format(hex(self.v))
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54
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55
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346
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56 def Mov(*args):
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57 if len(args) == 2:
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58 if isinstance(args[1], int):
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59 return Mov1(*args)
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60 elif isinstance(args[1], ArmRegister):
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61 return Mov2(*args)
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62 raise Exception()
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63
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64
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65 class Mov1(ArmInstruction):
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342
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66 """ Mov Rd, imm16 """
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67 def __init__(self, reg, imm):
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68 super().__init__()
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346
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69 assert type(imm) is int
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342
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70 self.reg = reg
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71 self.imm = imm
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72
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73 def encode(self):
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346
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74 self.token[0:12] = encode_imm32(self.imm)
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345
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75 self.token.Rd = self.reg.num
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342
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76 self.token[16:20] = 0
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346
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77 self.token[20] = 0 # Set flags
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342
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78 self.token[21:28] = 0b0011101
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346
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79 self.token.cond = AL
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342
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80 return self.token.encode()
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81
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82 def __repr__(self):
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345
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83 return 'Mov {}, {}'.format(self.reg, self.imm)
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84
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85
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346
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86 class Mov2(ArmInstruction):
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87 def __init__(self, rd, rm):
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88 super().__init__()
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89 self.rd = rd
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90 self.rm = rm
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91
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92 def encode(self):
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93 self.token[0:4] = self.rm.num
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94 self.token[4:12] = 0
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95 self.token[12:16] = self.rd.num
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96 self.token[16:20] = 0
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97 self.token.S = 0
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98 self.token[21:28] = 0xD
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99 self.token.cond = AL
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100 return self.token.encode()
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101
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350
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102 def __repr__(self):
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103 return 'MOV {}, {}'.format(self.rd, self.rm)
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104
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346
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105
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352
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106 def Cmp(*args):
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107 if len(args) == 2:
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108 if isinstance(args[1], int):
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109 return Cmp1(*args)
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110 elif isinstance(args[1], ArmRegister):
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111 return Cmp2(*args)
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112 raise Exception()
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113
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114
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115 class Cmp1(ArmInstruction):
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116 """ CMP Rn, imm """
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117 def __init__(self, reg, imm):
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118 super().__init__()
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119 assert type(imm) is int
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120 self.reg = reg
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121 self.imm = imm
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122
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123 def encode(self):
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124 self.token[0:12] = encode_imm32(self.imm)
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125 self.token.Rn = self.reg.num
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126 self.token[20:28] = 0b00110101
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127 self.token.cond = AL
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128 return self.token.encode()
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129
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130 def __repr__(self):
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131 return 'CMP {}, {}'.format(self.reg, self.imm)
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132
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133
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134 class Cmp2(ArmInstruction):
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135 """ CMP Rn, Rm """
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136 def __init__(self, rn, rm):
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137 super().__init__()
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138 self.rn = rn
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139 self.rm = rm
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140
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141 def encode(self):
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142 self.token.Rn = self.rn.num
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143 self.token.Rm = self.rm.num
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144 self.token[7:16] = 0
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145 self.token[20:28] = 0b10101
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146 self.token.cond = AL
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147 return self.token.encode()
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148
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149 def __repr__(self):
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150 return 'CMP {}, {}'.format(self.rn, self.rm)
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151
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152
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345
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153 def Add(*args):
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154 if len(args) == 3 and isinstance(args[0], ArmRegister) and \
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155 isinstance(args[1], ArmRegister):
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156 if isinstance(args[2], ArmRegister):
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157 return Add1(args[0], args[1], args[2])
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158 elif isinstance(args[2], int):
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159 return Add2(args[0], args[1], args[2])
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160 raise Exception()
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161
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162 def Sub(*args):
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163 if len(args) == 3 and isinstance(args[0], ArmRegister) and \
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164 isinstance(args[1], ArmRegister):
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165 if isinstance(args[2], ArmRegister):
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166 return Sub1(args[0], args[1], args[2])
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167 elif isinstance(args[2], int):
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168 return Sub2(args[0], args[1], args[2])
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169 raise Exception()
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170
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352
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171
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346
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172 def Mul(*args):
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173 return Mul1(args[0], args[1], args[2])
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174
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175
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354
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176 class Mul1(ArmInstruction):
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346
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177 def __init__(self, rd, rn, rm):
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178 super().__init__()
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179 self.rd = rd
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180 self.rn = rn
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181 self.rm = rm
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182
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183 def encode(self):
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184 self.token[0:4] = self.rn.num
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185 self.token[4:8] = 0b1001
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186 self.token[8:12] = self.rm.num
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187 self.token[16:20] = self.rd.num
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188 self.token.S = 0
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189 self.token.cond = AL
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190 return self.token.encode()
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191
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192
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345
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193 class OpRegRegReg(ArmInstruction):
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194 """ add rd, rn, rm """
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195 def __init__(self, rd, rn, rm, shift=0):
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196 super().__init__()
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197 self.rd = rd
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198 self.rn = rn
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199 self.rm = rm
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200
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201 def encode(self):
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202 self.token[0:4] = self.rm.num
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203 self.token[4] = 0
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204 self.token[5:7] = 0
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205 self.token[7:12] = 0 # Shift
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206 self.token.Rd = self.rd.num
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207 self.token.Rn = self.rn.num
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208 self.token.S = 0 # Set flags
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209 self.token[21:28] = self.opcode
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210 self.token.cond = 0xE # Always!
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211 return self.token.encode()
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212
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213 def __repr__(self):
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354
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214 return '{} {}, {}, {}'.format(self.mnemonic, self.rd, self.rn, self.rm)
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345
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215
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216
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217 class Add1(OpRegRegReg):
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354
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218 mnemonic = 'ADD'
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345
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219 opcode = 0b0000100
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220
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221
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222 class Sub1(OpRegRegReg):
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354
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223 mnemonic = 'SUB'
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345
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224 opcode = 0b0000010
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225
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226
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227 class Orr1(OpRegRegReg):
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354
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228 mnemonic = 'ORR'
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345
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229 opcode = 0b0001100
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230
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342
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231
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356
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232 class And1(OpRegRegReg):
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233 mnemonic = 'AND'
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234 opcode = 0b0000000
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235
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236
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237 class ShiftBase(ArmInstruction):
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238 """ ? rd, rn, rm """
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239 def __init__(self, rd, rn, rm):
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240 super().__init__()
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241 self.rd = rd
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242 self.rn = rn
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243 self.rm = rm
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244
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245 def encode(self):
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246 self.token[0:4] = self.rn.num
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247 self.token[4:8] = self.opcode
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248 self.token[8:12] = self.rm.num
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249 self.token[12:16] = self.rd.num
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250 self.token.S = 0 # Set flags
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251 self.token[21:28] = 0b1101
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252 self.token.cond = 0xE # Always!
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253 return self.token.encode()
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254
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255 def __repr__(self):
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256 return '{} {}, {}, {}'.format(self.mnemonic, self.rd, self.rn, self.rm)
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257
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258
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259 class Lsr1(ShiftBase):
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260 mnemonic = 'LSR'
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261 opcode = 0b0011
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262
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263
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264 class Lsl1(ShiftBase):
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265 mnemonic = 'LSL'
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266 opcode = 0b0001
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267
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268
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345
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269 class OpRegRegImm(ArmInstruction):
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270 """ add rd, rn, imm12 """
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271 def __init__(self, rd, rn, imm):
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272 super().__init__()
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273 self.rd = rd
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274 self.rn = rn
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275 self.imm2 = encode_imm32(imm)
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276 self.imm = imm
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277
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278 def encode(self):
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279 self.token[0:12] = self.imm2
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280 self.token.Rd = self.rd.num
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281 self.token.Rn = self.rn.num
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282 self.token.S = 0 # Set flags
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283 self.token[21:28] = self.opcode
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284 self.token.cond = 0xE # Always!
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285 return self.token.encode()
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286
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287 def __repr__(self):
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354
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288 return '{} {}, {}, {}'.format(self.mnemonic, self.rd, self.rn, self.imm)
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345
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289
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290
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291 class Add2(OpRegRegImm):
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354
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292 mnemonic = 'ADD'
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345
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293 opcode = 0b0010100
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294
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295
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296 class Sub2(OpRegRegImm):
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354
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297 mnemonic = 'SUB'
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345
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298 opcode = 0b0010010
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299
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300
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301
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302 # Branches:
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303
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304 class BranchBaseRoot(ArmInstruction):
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305 def __init__(self, target):
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306 super().__init__()
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307 self.target = target
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308
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309 def encode(self):
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310 self.token.cond = self.cond
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311 self.token[24:28] = self.opcode
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312 return self.token.encode()
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313
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314 def relocations(self):
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315 return [(self.target, 'b_imm24')]
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316
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350
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317 def __repr__(self):
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318 mnemonic = self.__class__.__name__
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319 return '{} {}'.format(mnemonic, self.target)
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320
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345
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321
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346
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322 EQ, NE, CS, CC, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL = range(15)
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323
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345
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324 class BranchBase(BranchBaseRoot):
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325 opcode = 0b1010
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326
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327 class BranchLinkBase(BranchBaseRoot):
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328 opcode = 0b1011
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329
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330 class Bl(BranchLinkBase):
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346
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331 cond = AL
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345
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332
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333 class B(BranchBase):
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346
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334 cond = AL
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345
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335
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336 class Beq(BranchBase):
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346
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337 cond = EQ
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345
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338
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339 class Bgt(BranchBase):
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346
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340 cond = GT
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345
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341
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342 class Ble(BranchBase):
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346
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343 cond = LE
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344
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345 class Blt(BranchBase):
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346 cond = LT
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347
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352
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348 class Bne(BranchBase):
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349 cond = NE
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346
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350
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351 # Memory:
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352
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353 def reg_list_to_mask(reg_list):
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354 mask = 0
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355 for reg in reg_list:
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356 mask |= (1 << reg.num)
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357 return mask
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358
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359
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360 class Push(ArmInstruction):
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361 def __init__(self, register_set):
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362 super().__init__()
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363 self.reg_list = register_set
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364
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365 def encode(self):
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366 self.token.cond = AL
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367 self.token[16:28] = 0b100100101101
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368 reg_list = 0
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369 self.token[0:16] = reg_list_to_mask(self.reg_list)
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370 return self.token.encode()
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371
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350
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372 def __repr__(self):
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373 return 'PUSH {}'.format(self.reg_list)
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374
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375
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346
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376 class Pop(ArmInstruction):
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377 def __init__(self, register_set):
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378 super().__init__()
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379 self.reg_list = register_set
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380
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381 def encode(self):
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382 self.token.cond = AL
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383 self.token[16:28] = 0b100010111101
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384 self.token[0:16] = reg_list_to_mask(self.reg_list)
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385 return self.token.encode()
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345
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386
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350
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387 def __repr__(self):
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388 return 'POP {}'.format(self.reg_list)
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389
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345
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390
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346
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391 def Ldr(*args):
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350
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392 """ Convenience function that creates the correct instruction """
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393 if len(args) == 3:
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394 if isinstance(args[1], ArmRegister):
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395 return Ldr1(*args)
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396 elif len(args) == 2:
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397 if isinstance(args[1], ArmRegister):
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398 return Ldr1(args[0], args[1], 0)
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399 elif isinstance(args[1], str):
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400 return Ldr3(*args)
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346
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401 raise Exception()
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402
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350
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403
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346
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404 def Str(*args):
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405 if len(args) == 3 and isinstance(args[1], ArmRegister):
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406 return Str1(*args)
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407 elif len(args) == 2 and isinstance(args[1], ArmRegister):
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408 return Str1(args[0], args[1], 0)
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409 raise Exception()
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410
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411
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412 class LdrStrBase(ArmInstruction):
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413 def __init__(self, rt, rn, offset):
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414 super().__init__()
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415 self.rt = rt
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416 self.rn = rn
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417 self.offset = offset
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418
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419 def encode(self):
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420 self.token.cond = AL
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421 self.token.Rn = self.rn.num
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422 self.token[25:28] = self.opcode
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423 self.token[20] = self.bit20
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424 self.token[12:16] = self.rt.num
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425 self.token[24] = 1 # Index
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426 if self.offset >= 0:
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427 self.token[23] = 1 # U == 1 'add'
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428 self.token[0:12] = self.offset
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429 else:
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430 self.token[23] = 0
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431 self.token[0:12] = -self.offset
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432 return self.token.encode()
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433
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350
|
434 def __repr__(self):
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435 return '{} {}, [{}, {}]'.format(self.mnemonic, self.rt, self.rn,
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|
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436 hex(self.offset))
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346
|
437
|
|
354
|
438
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346
|
439 class Str1(LdrStrBase):
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440 opcode = 0b010
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441 bit20 = 0
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350
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442 mnemonic = 'STR'
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346
|
443
|
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444
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|
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445 class Ldr1(LdrStrBase):
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446 opcode = 0b010
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|
|
447 bit20 = 1
|
|
350
|
448 mnemonic = 'LDR'
|
|
346
|
449
|
|
|
450
|
|
354
|
451 class Adr(ArmInstruction):
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|
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452 def __init__(self, rd, label):
|
|
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453 super().__init__()
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|
454 self.rd = rd
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455 self.label = label
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456
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|
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457 def __repr__(self):
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|
|
458 return 'ADR {}, {}'.format(self.rd, self.label)
|
|
|
459
|
|
|
460 def relocations(self):
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|
|
461 return [(self.label, 'adr_imm12')]
|
|
|
462
|
|
|
463 def encode(self):
|
|
|
464 self.token.cond = AL
|
|
|
465 self.token[0:12] = 0 # Filled by linker
|
|
|
466 self.token[12:16] = self.rd.num
|
|
|
467 self.token[16:20] = 0b1111
|
|
|
468 self.token[25] = 1
|
|
|
469 return self.token.encode()
|
|
|
470
|
|
|
471
|
|
346
|
472 class Ldr3(ArmInstruction):
|
|
350
|
473 """ Load PC relative constant value
|
|
|
474 LDR rt, label
|
|
|
475 encoding A1
|
|
|
476 """
|
|
346
|
477 def __init__(self, rt, label):
|
|
350
|
478 super().__init__()
|
|
346
|
479 self.rt = rt
|
|
|
480 self.label = label
|
|
|
481
|
|
350
|
482 def __repr__(self):
|
|
|
483 return 'LDR {}, {}'.format(self.rt, self.label)
|
|
|
484
|
|
|
485 def relocations(self):
|
|
|
486 return [(self.label, 'ldr_imm12')]
|
|
|
487
|
|
|
488 def encode(self):
|
|
|
489 self.token.cond = AL
|
|
|
490 self.token[0:12] = 0 # Filled by linker
|
|
|
491 self.token[12:16] = self.rt.num
|
|
|
492 self.token[16:23] = 0b0011111
|
|
|
493 self.token[24:28] = 0b0101
|
|
|
494 return self.token.encode()
|
