annotate python/stlink.py @ 196:ec2b423cdbea

Merge asm and asmlib files
author Windel Bouwman
date Sat, 01 Jun 2013 11:55:49 +0200
parents c694ec551f34
children
rev   line source
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1 import struct, time
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2 from usb import UsbContext, UsbDevice
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3 from devices import Interface, STLinkException, registerInterface
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4 import adi
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5
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6 """
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7 More or less copied from:
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8 https://github.com/texane/stlink
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9 Tracing from:
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10 https://github.com/obe1line/stlink-trace
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11
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12 """
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13 ST_VID, STLINK2_PID = 0x0483, 0x3748
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14
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15 def checkDevice(device):
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16 return device.VendorId == ST_VID and device.ProductId == STLINK2_PID
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17
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18 DFU_MODE, MASS_MODE, DEBUG_MODE = 0, 1, 2
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19
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20 CORE_RUNNING = 0x80
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21 CORE_HALTED = 0x81
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22
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23 # Commands:
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24 GET_VERSION = 0xf1
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25 DEBUG_COMMAND = 0xf2
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26 DFU_COMMAND = 0xf3
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27 GET_CURRENT_MODE = 0xf5
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28
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29 # dfu commands:
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30 DFU_EXIT = 0x7
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31
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32 # debug commands:
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33 DEBUG_ENTER = 0x20
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34 DEBUG_EXIT = 0x21
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35 DEBUG_ENTER_SWD = 0xa3
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36 DEBUG_GETSTATUS = 0x01
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37 DEBUG_FORCEDEBUG = 0x02
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38 DEBUG_RESETSYS = 0x03
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39 DEBUG_READALLREGS = 0x04
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40 DEBUG_READREG = 0x5
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41 DEBUG_WRITEREG = 0x6
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42 DEBUG_READMEM_32BIT = 0x7
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43 DEBUG_WRITEMEM_32BIT = 0x8
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44 DEBUG_RUNCORE = 0x9
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45 DEBUG_STEPCORE = 0xa
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46
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47 JTAG_WRITEDEBUG_32BIT = 0x35
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48 JTAG_READDEBUG_32BIT = 0x36
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49 TRACE_GET_BYTE_COUNT = 0x42
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50
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51 # cortex M3
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52 CM3_REG_CPUID = 0xE000ED00
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53
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54 @registerInterface((ST_VID, STLINK2_PID))
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55 class STLink2(Interface):
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56 """ STlink2 interface implementation. """
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57 def __init__(self, stlink2=None):
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58 self.devHandle = None
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59 if not stlink2:
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60 context = UsbContext()
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61 stlink2s = list(filter(checkDevice, context.DeviceList))
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62 if not stlink2s:
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63 raise STLinkException('Could not find an ST link 2 interface')
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64 if len(stlink2s) > 1:
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65 print('More then one stlink2 found, picking first one')
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66 stlink2 = stlink2s[0]
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67 assert isinstance(stlink2, UsbDevice) # Nifty type checking
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68 assert checkDevice(stlink2)
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69 self.stlink2 = stlink2
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70 def __del__(self):
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71 if self.IsOpen:
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72 if self.CurrentMode == DEBUG_MODE:
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73 self.exitDebugMode()
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74 self.close()
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75 def __str__(self):
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76 if self.IsOpen:
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77 return 'STlink2 device version {0}'.format(self.Version)
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78 else:
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79 return 'STlink2 device'
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80 def open(self):
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81 if self.IsOpen:
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82 return
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83 self.devHandle = self.stlink2.open()
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84 if self.devHandle.Configuration != 1:
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85 self.devHandle.Configuration = 1
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86 self.devHandle.claimInterface(0)
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87
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88 # First initialization:
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89 if self.CurrentMode == DFU_MODE:
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90 self.exitDfuMode()
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91 if self.CurrentMode != DEBUG_MODE:
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92 self.enterSwdMode()
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93 #self.reset()
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94 def close(self):
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95 if self.IsOpen:
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96 self.devHandle.close()
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97 self.devHandle = None
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98 @property
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99 def IsOpen(self):
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100 return self.devHandle != None
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101 # modes:
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102 def getCurrentMode(self):
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103 cmd = bytearray(16)
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104 cmd[0] = GET_CURRENT_MODE
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105 reply = self.send_recv(cmd, 2) # Expect 2 bytes back
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106 return reply[0]
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107 CurrentMode = property(getCurrentMode)
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108 @property
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109 def CurrentModeString(self):
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110 modes = {DFU_MODE: 'dfu', MASS_MODE: 'massmode', DEBUG_MODE:'debug'}
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111 return modes[self.CurrentMode]
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112 def exitDfuMode(self):
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113 cmd = bytearray(16)
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114 cmd[0:2] = DFU_COMMAND, DFU_EXIT
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115 self.send_recv(cmd)
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116 def enterSwdMode(self):
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117 cmd = bytearray(16)
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118 cmd[0:3] = DEBUG_COMMAND, DEBUG_ENTER, DEBUG_ENTER_SWD
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119 self.send_recv(cmd)
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120 def exitDebugMode(self):
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121 cmd = bytearray(16)
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122 cmd[0:2] = DEBUG_COMMAND, DEBUG_EXIT
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123 self.send_recv(cmd)
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124
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125 def getVersion(self):
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126 cmd = bytearray(16)
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127 cmd[0] = GET_VERSION
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128 data = self.send_recv(cmd, 6) # Expect 6 bytes back
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129 # Parse 6 bytes into various versions:
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130 b0, b1, b2, b3, b4, b5 = data
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131 stlink_v = b0 >> 4
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132 jtag_v = ((b0 & 0xf) << 2) | (b1 >> 6)
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133 swim_v = b1 & 0x3f
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134 vid = (b3 << 8) | b2
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135 pid = (b5 << 8) | b4
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136 return 'stlink={0} jtag={1} swim={2} vid:pid={3:04X}:{4:04X}'.format(\
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137 stlink_v, jtag_v, swim_v, vid, pid)
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138 Version = property(getVersion)
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139
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140 @property
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141 def ChipId(self):
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142 return self.read_debug32(0xE0042000)
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143 @property
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144 def CpuId(self):
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145 u32 = self.read_debug32(CM3_REG_CPUID)
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146 implementer_id = (u32 >> 24) & 0x7f
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147 variant = (u32 >> 20) & 0xf
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148 part = (u32 >> 4) & 0xfff
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149 revision = u32 & 0xf
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150 return implementer_id, variant, part, revision
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151 def getStatus(self):
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152 cmd = bytearray(16)
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153 cmd[0:2] = DEBUG_COMMAND, DEBUG_GETSTATUS
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154 reply = self.send_recv(cmd, 2)
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155 return reply[0]
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156 Status = property(getStatus)
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157 @property
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158 def StatusString(self):
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159 s = self.Status
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160 statii = {CORE_RUNNING: 'CORE RUNNING', CORE_HALTED: 'CORE HALTED'}
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161 if s in statii:
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162 return statii[s]
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163 return 'Unknown status'
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164
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165 def reset(self):
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166 cmd = bytearray(16)
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167 cmd[0:2] = DEBUG_COMMAND, DEBUG_RESETSYS
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168 self.send_recv(cmd, 2)
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169
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170 # debug commands:
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171 def step(self):
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172 cmd = bytearray(16)
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173 cmd[0:2] = DEBUG_COMMAND, DEBUG_STEPCORE
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174 self.send_recv(cmd, 2)
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175 def run(self):
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176 cmd = bytearray(16)
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177 cmd[0:2] = DEBUG_COMMAND, DEBUG_RUNCORE
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178 self.send_recv(cmd, 2)
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179 def halt(self):
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180 cmd = bytearray(16)
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181 cmd[0:2] = DEBUG_COMMAND, DEBUG_FORCEDEBUG
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182 self.send_recv(cmd, 2)
178
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183
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184 # Tracing:
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185 def traceEnable(self):
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186 self.write_debug32(0xE000EDF0, 0xA05F0003)
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187
178
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188 # Enable TRCENA:
144
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189 DEMCR = 0xE000EDFC
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190 v = self.read_debug32(DEMCR)
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191 v |= (1 << 24)
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192 self.write_debug32(DEMCR, v)
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193
178
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194 # ?? Enable write??
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195 self.write_debug32(0xE0002000, 0x2) #
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196
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197 # DBGMCU_CR:
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198 self.write_debug32(0xE0042004, 0x27) # Enable trace in async mode
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199
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200 # TPIU config:
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201 self.write_debug32(0xE0040004, 0x00000001) # current port size register --> 1 == port size = 1
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202 self.write_debug32(0xE0040010, 0x23) # random clock divider??
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203 self.write_debug32(0xE00400F0, 0x2) # selected pin protocol (2 == NRZ)
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204 self.write_debug32(0xE0040304, 0x100) # continuous formatting
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205
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206 # ITM config:
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207 self.write_debug32(0xE0000FB0, 0xC5ACCE55) # Unlock write access to ITM
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208 self.write_debug32(0xE0000F80, 0x00010005) # ITM Enable, sync enable, ATB=1
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209 self.write_debug32(0xE0000E00, 0xFFFFFFFF) # Enable all trace ports in ITM
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210 self.write_debug32(0xE0000E40, 0x0000000F) # Set privilege mask for all 32 ports.
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211 def writePort0(self, v32):
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212 self.write_debug32(0xE0000000, v32)
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213 def getTraceByteCount(self):
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214 cmd = bytearray(16)
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215 cmd[0:2] = DEBUG_COMMAND, 0x42
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216 reply = self.send_recv(cmd, 2)
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217 return struct.unpack('<H', reply[0:2])[0]
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218 def readTraceData(self):
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219 bsize = self.getTraceByteCount()
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220 if bsize > 0:
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221 td = self.recv_ep3(bsize)
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222 print(td)
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223 else:
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224 print('no trace data')
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225
114
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226 # Helper 1 functions:
115
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227 def write_debug32(self, address, value):
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228 cmd = bytearray(16)
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229 cmd[0:2] = DEBUG_COMMAND, JTAG_WRITEDEBUG_32BIT
119
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230 cmd[2:10] = struct.pack('<II', address, value)
178
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231 r = self.send_recv(cmd, 2)
114
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232 def read_debug32(self, address):
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233 cmd = bytearray(16)
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234 cmd[0:2] = DEBUG_COMMAND, JTAG_READDEBUG_32BIT
114
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235 cmd[2:6] = struct.pack('<I', address) # pack into u32 little endian
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236 reply = self.send_recv(cmd, 8)
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237 return struct.unpack('<I', reply[4:8])[0]
115
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238 def write_reg(self, reg, value):
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239 cmd = bytearray(16)
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240 cmd[0:3] = DEBUG_COMMAND, DEBUG_WRITEREG, reg
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241 cmd[3:7] = struct.pack('<I', value)
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242 r = self.send_recv(cmd, 2)
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243 def read_reg(self, reg):
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244 cmd = bytearray(16)
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245 cmd[0:3] = DEBUG_COMMAND, DEBUG_READREG, reg
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246 reply = self.send_recv(cmd, 4)
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247 return struct.unpack('<I', reply)[0]
124
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248 def read_all_regs(self):
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249 cmd = bytearray(16)
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250 cmd[0:2] = DEBUG_COMMAND, DEBUG_READALLREGS
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251 reply = self.send_recv(cmd, 84)
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252 fmt = '<' + 'I' * 21 # unpack 21 register values
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253 return list(struct.unpack(fmt, reply))
116
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254 def write_mem32(self, address, content):
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255 assert len(content) % 4 == 0
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256 cmd = bytearray(16)
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257 cmd[0:2] = DEBUG_COMMAND, DEBUG_WRITEMEM_32BIT
119
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258 cmd[2:8] = struct.pack('<IH', address, len(content))
116
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259 self.send_recv(cmd)
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260 self.send_recv(content)
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261 def read_mem32(self, address, length):
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262 assert length % 4 == 0
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263 cmd = bytearray(16)
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264 cmd[0:2] = DEBUG_COMMAND, DEBUG_READMEM_32BIT
119
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265 cmd[2:8] = struct.pack('<IH', address, length)
115
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266 reply = self.send_recv(cmd, length) # expect memory back!
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267 return reply
114
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268
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269 # Helper 2 functions:
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270 def send_recv(self, tx, rxsize=0):
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271 """ Helper function that transmits and receives data in bulk mode. """
114
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272 # TODO: we could use here the non-blocking libusb api.
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273 tx = bytes(tx)
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274 #assert len(tx) == 16
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275 self.devHandle.bulkWrite(2, tx) # write to endpoint 2
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276 if rxsize > 0:
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277 return self.devHandle.bulkRead(1, rxsize) # read from endpoint 1
178
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278 def recv_ep3(self, rxsize):
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279 return self.devHandle.bulkRead(3, rxsize)
114
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280
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281 if __name__ == '__main__':
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282 # Test program
128
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283 sl = STLink2()
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284 sl.open()
132
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285 sl.reset()
114
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286 print('version:', sl.Version)
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287 print('mode before doing anything:', sl.CurrentModeString)
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288 if sl.CurrentMode == DFU_MODE:
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289 sl.exitDfuMode()
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290 sl.enterSwdMode()
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291 print('mode after entering swd mode:', sl.CurrentModeString)
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292
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293 i = sl.ChipId
129
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294 print('chip id: 0x{0:X}'.format(i))
114
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295 print('cpu: {0}'.format(sl.CpuId))
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296
117
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297 print('status: {0}'.format(sl.StatusString))
114
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298
115
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299 # test registers:
124
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300 sl.write_reg(0, 0xdeadbeef)
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301 sl.write_reg(1, 0xcafebabe)
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302 sl.write_reg(2, 0xc0ffee)
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303 sl.write_reg(3, 0x1337)
124
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304 sl.write_reg(5, 0x1332)
117
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305 sl.write_reg(6, 0x12345)
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306 assert sl.read_reg(3) == 0x1337
124
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307 assert sl.read_reg(5) == 0x1332
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diff changeset
308 assert sl.read_reg(6) == 0x12345
124
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309 regs = sl.read_all_regs()
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310 for i in range(len(regs)):
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311 print('R{0}=0x{1:X}'.format(i, regs[i]))
178
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312
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313 print('tracing')
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314 sl.traceEnable()
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315 sl.run()
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316 sl.writePort0(0x1337) # For test
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317 time.sleep(0.1)
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318 td = sl.readTraceData()
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319 print('trace data:', td)
144
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320
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321 # Test CoreSight registers:
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322 idr4 = sl.read_debug32(0xE0041fd0)
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323 print('idr4 =', idr4)
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324
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325 print('== ADI ==')
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326 a = adi.Adi(sl)
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327 a.parseRomTable(0xE00FF000) # why is rom table at 0xE00FF000?
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328 print('== ADI ==')
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329
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330 # Detect ROM table:
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331 id4 = sl.read_debug32(0xE00FFFD0)
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332 id5 = sl.read_debug32(0xE00FFFD4)
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333 id6 = sl.read_debug32(0xE00FFFD8)
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diff changeset
334 id7 = sl.read_debug32(0xE00FFFDC)
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diff changeset
335 id0 = sl.read_debug32(0xE00FFFE0)
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336 id1 = sl.read_debug32(0xE00FFFE4)
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337 id2 = sl.read_debug32(0xE00FFFE8)
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338 id3 = sl.read_debug32(0xE00FFFEC)
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339 pIDs = [id0, id1, id2, id3, id4, id5, id6, id7]
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340 print(pIDs)
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341
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diff changeset
342 print('reading from 0xE00FF000')
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343 scs = sl.read_debug32(0xE00FF000)
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344 print('scs {0:08X}'.format(scs))
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diff changeset
345 dwt = sl.read_debug32(0xE00FF004)
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346 print('dwt {0:08X}'.format(dwt))
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diff changeset
347 fpb = sl.read_debug32(0xE00FF008)
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348 print('fpb {0:08X}'.format(fpb))
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diff changeset
349 itm = sl.read_debug32(0xE00FF00C)
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diff changeset
350 print('itm {0:08X}'.format(itm))
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diff changeset
351 tpiu = sl.read_debug32(0xE00FF010)
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diff changeset
352 print('tpiu {0:08X}'.format(tpiu))
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diff changeset
353 etm = sl.read_debug32(0xE00FF014)
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diff changeset
354 print('etm {0:08X}'.format(etm))
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355 assert sl.read_debug32(0xE00FF018) == 0x0 # end marker
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356
59a9a499e518 Added adi class
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357 devid = sl.read_debug32(0xE0040FC8)
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358 print('TPIU_DEVID: {0:X}'.format(devid))
59a9a499e518 Added adi class
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359 devtype = sl.read_debug32(0xE0040FCC)
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360 print('TPIU_TYPEID: {0:X}'.format(devtype))
114
f42268da614f Connected to stm32f4discovery
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361
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362 sl.exitDebugMode()
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363 print('mode at end:', sl.CurrentModeString)
f42268da614f Connected to stm32f4discovery
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364
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365 sl.close()
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f51791638cae Simplified flashing
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366 print('Test succes!')
114
f42268da614f Connected to stm32f4discovery
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parents: 113
diff changeset
367