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114
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1 import struct, time
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129
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2 from usb import UsbContext, UsbDevice
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128
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3 from devices import Interface, STLinkException, registerInterface
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4
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5 ST_VID, STLINK2_PID = 0x0483, 0x3748
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6
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7 def checkDevice(device):
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8 return device.VendorId == ST_VID and device.ProductId == STLINK2_PID
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9
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10 DFU_MODE, MASS_MODE, DEBUG_MODE = 0, 1, 2
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11
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12 CORE_RUNNING = 0x80
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13 CORE_HALTED = 0x81
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14
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114
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15 # Commands:
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16 GET_VERSION = 0xf1
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17 DEBUG_COMMAND = 0xf2
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18 DFU_COMMAND = 0xf3
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19 GET_CURRENT_MODE = 0xf5
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20
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21 # dfu commands:
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22 DFU_EXIT = 0x7
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23
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24 # debug commands:
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25 DEBUG_ENTER = 0x20
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26 DEBUG_EXIT = 0x21
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27 DEBUG_ENTER_SWD = 0xa3
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28 DEBUG_GETSTATUS = 0x01
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29 DEBUG_FORCEDEBUG = 0x02
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30 DEBUG_RESETSYS = 0x03
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31 DEBUG_READALLREGS = 0x04
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32 DEBUG_READREG = 0x5
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33 DEBUG_WRITEREG = 0x6
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34 DEBUG_READMEM_32BIT = 0x7
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35 DEBUG_WRITEMEM_32BIT = 0x8
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36 DEBUG_RUNCORE = 0x9
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37 DEBUG_STEPCORE = 0xa
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38
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39 JTAG_WRITEDEBUG_32BIT = 0x35
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40 JTAG_READDEBUG_32BIT = 0x36
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41
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42 # cortex M3
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43 CM3_REG_CPUID = 0xE000ED00
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44
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128
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45 @registerInterface((ST_VID, STLINK2_PID))
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46 class STLink2(Interface):
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47 """ STlink2 interface implementation. """
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48 def __init__(self, stlink2=None):
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49 self.devHandle = None
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50 if not stlink2:
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51 context = UsbContext()
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52 stlink2s = list(filter(checkDevice, context.DeviceList))
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53 if not stlink2s:
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54 raise STLinkException('Could not find an ST link 2 interface')
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55 if len(stlink2s) > 1:
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56 print('More then one stlink2 found, picking first one')
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57 stlink2 = stlink2s[0]
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129
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58 assert isinstance(stlink2, UsbDevice) # Nifty type checking
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59 assert checkDevice(stlink2)
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60 self.stlink2 = stlink2
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61 def __del__(self):
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62 if self.IsOpen:
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63 if self.CurrentMode == DEBUG_MODE:
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64 self.exitDebugMode()
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65 self.close()
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66 def __str__(self):
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67 if self.IsOpen:
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68 return 'STlink2 device version {0}'.format(self.Version)
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69 else:
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70 return 'STlink2 device'
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71 def open(self):
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72 if self.IsOpen:
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73 return
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74 self.devHandle = self.stlink2.open()
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75 if self.devHandle.Configuration != 1:
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76 self.devHandle.Configuration = 1
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77 self.devHandle.claimInterface(0)
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78
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79 # First initialization:
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80 if self.CurrentMode == DFU_MODE:
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81 self.exitDfuMode()
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82 if self.CurrentMode != DEBUG_MODE:
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83 self.enterSwdMode()
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132
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84 #self.reset()
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85 def close(self):
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86 if self.IsOpen:
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87 self.devHandle.close()
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88 self.devHandle = None
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89 @property
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90 def IsOpen(self):
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91 return self.devHandle != None
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115
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92 # modes:
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93 def getCurrentMode(self):
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94 cmd = bytearray(16)
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95 cmd[0] = GET_CURRENT_MODE
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96 reply = self.send_recv(cmd, 2) # Expect 2 bytes back
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97 return reply[0]
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98 CurrentMode = property(getCurrentMode)
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99 @property
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100 def CurrentModeString(self):
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101 modes = {DFU_MODE: 'dfu', MASS_MODE: 'massmode', DEBUG_MODE:'debug'}
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102 return modes[self.CurrentMode]
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103 def exitDfuMode(self):
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104 cmd = bytearray(16)
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105 cmd[0:2] = DFU_COMMAND, DFU_EXIT
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106 self.send_recv(cmd)
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107 def enterSwdMode(self):
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108 cmd = bytearray(16)
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109 cmd[0:3] = DEBUG_COMMAND, DEBUG_ENTER, DEBUG_ENTER_SWD
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110 self.send_recv(cmd)
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111 def exitDebugMode(self):
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112 cmd = bytearray(16)
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113 cmd[0:2] = DEBUG_COMMAND, DEBUG_EXIT
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114 self.send_recv(cmd)
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115
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116 def getVersion(self):
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117 cmd = bytearray(16)
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118 cmd[0] = GET_VERSION
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119 data = self.send_recv(cmd, 6) # Expect 6 bytes back
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120 # Parse 6 bytes into various versions:
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121 b0, b1, b2, b3, b4, b5 = data
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122 stlink_v = b0 >> 4
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123 jtag_v = ((b0 & 0xf) << 2) | (b1 >> 6)
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124 swim_v = b1 & 0x3f
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125 vid = (b3 << 8) | b2
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126 pid = (b5 << 8) | b4
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127 return 'stlink={0} jtag={1} swim={2} vid:pid={3:04X}:{4:04X}'.format(\
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128 stlink_v, jtag_v, swim_v, vid, pid)
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129 Version = property(getVersion)
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130
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131 @property
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132 def ChipId(self):
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133 return self.read_debug32(0xE0042000)
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134 @property
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135 def CpuId(self):
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136 u32 = self.read_debug32(CM3_REG_CPUID)
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137 implementer_id = (u32 >> 24) & 0x7f
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138 variant = (u32 >> 20) & 0xf
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139 part = (u32 >> 4) & 0xfff
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140 revision = u32 & 0xf
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141 return implementer_id, variant, part, revision
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142 def getStatus(self):
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143 cmd = bytearray(16)
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144 cmd[0:2] = DEBUG_COMMAND, DEBUG_GETSTATUS
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145 reply = self.send_recv(cmd, 2)
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146 return reply[0]
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147 Status = property(getStatus)
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148 @property
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149 def StatusString(self):
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150 s = self.Status
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151 statii = {CORE_RUNNING: 'CORE RUNNING', CORE_HALTED: 'CORE HALTED'}
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152 if s in statii:
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153 return statii[s]
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154 return 'Unknown status'
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155
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156 def reset(self):
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157 cmd = bytearray(16)
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158 cmd[0:2] = DEBUG_COMMAND, DEBUG_RESETSYS
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159 self.send_recv(cmd, 2)
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160
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115
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161 # debug commands:
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162 def step(self):
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163 cmd = bytearray(16)
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164 cmd[0:2] = DEBUG_COMMAND, DEBUG_STEPCORE
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165 self.send_recv(cmd, 2)
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166 def run(self):
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167 cmd = bytearray(16)
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168 cmd[0:2] = DEBUG_COMMAND, DEBUG_RUNCORE
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169 self.send_recv(cmd, 2)
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170 def halt(self):
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171 cmd = bytearray(16)
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172 cmd[0:2] = DEBUG_COMMAND, DEBUG_FORCEDEBUG
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173 self.send_recv(cmd, 2)
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174
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114
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175 # Helper 1 functions:
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176 def write_debug32(self, address, value):
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177 cmd = bytearray(16)
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178 cmd[0:2] = DEBUG_COMMAND, JTAG_WRITEDEBUG_32BIT
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179 cmd[2:10] = struct.pack('<II', address, value)
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180 self.send_recv(cmd, 2)
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181 def read_debug32(self, address):
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182 cmd = bytearray(16)
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183 cmd[0:2] = DEBUG_COMMAND, JTAG_READDEBUG_32BIT
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184 cmd[2:6] = struct.pack('<I', address) # pack into u32 little endian
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185 reply = self.send_recv(cmd, 8)
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186 return struct.unpack('<I', reply[4:8])[0]
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187 def write_reg(self, reg, value):
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188 cmd = bytearray(16)
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189 cmd[0:3] = DEBUG_COMMAND, DEBUG_WRITEREG, reg
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190 cmd[3:7] = struct.pack('<I', value)
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191 r = self.send_recv(cmd, 2)
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192 def read_reg(self, reg):
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193 cmd = bytearray(16)
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194 cmd[0:3] = DEBUG_COMMAND, DEBUG_READREG, reg
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195 reply = self.send_recv(cmd, 4)
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196 return struct.unpack('<I', reply)[0]
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124
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197 def read_all_regs(self):
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198 cmd = bytearray(16)
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199 cmd[0:2] = DEBUG_COMMAND, DEBUG_READALLREGS
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200 reply = self.send_recv(cmd, 84)
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201 fmt = '<' + 'I' * 21 # unpack 21 register values
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202 return list(struct.unpack(fmt, reply))
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203 def write_mem32(self, address, content):
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204 assert len(content) % 4 == 0
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205 cmd = bytearray(16)
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206 cmd[0:2] = DEBUG_COMMAND, DEBUG_WRITEMEM_32BIT
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207 cmd[2:8] = struct.pack('<IH', address, len(content))
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208 self.send_recv(cmd)
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209 self.send_recv(content)
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210 def read_mem32(self, address, length):
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211 assert length % 4 == 0
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212 cmd = bytearray(16)
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213 cmd[0:2] = DEBUG_COMMAND, DEBUG_READMEM_32BIT
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214 cmd[2:8] = struct.pack('<IH', address, length)
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215 reply = self.send_recv(cmd, length) # expect memory back!
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216 return reply
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217
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218 # Helper 2 functions:
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219 def send_recv(self, tx, rxsize=0):
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220 """ Helper function that transmits and receives data in bulk mode. """
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221 # TODO: we could use here the non-blocking libusb api.
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222 tx = bytes(tx)
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223 #assert len(tx) == 16
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224 self.devHandle.bulkWrite(2, tx) # write to endpoint 2
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225 if rxsize > 0:
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226 return self.devHandle.bulkRead(1, rxsize) # read from endpoint 1
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227
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228 if __name__ == '__main__':
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229 # Test program
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230 sl = STLink2()
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231 sl.open()
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132
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232 sl.reset()
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233 print('version:', sl.Version)
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234 print('mode before doing anything:', sl.CurrentModeString)
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235 if sl.CurrentMode == DFU_MODE:
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236 sl.exitDfuMode()
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237 sl.enterSwdMode()
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238 print('mode after entering swd mode:', sl.CurrentModeString)
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239
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240 i = sl.ChipId
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241 print('chip id: 0x{0:X}'.format(i))
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242 print('cpu: {0}'.format(sl.CpuId))
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243
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244 print('status: {0}'.format(sl.StatusString))
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245
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246 # test registers:
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247 sl.write_reg(0, 0xdeadbeef)
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248 sl.write_reg(1, 0xcafebabe)
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249 sl.write_reg(2, 0xc0ffee)
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250 sl.write_reg(3, 0x1337)
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251 sl.write_reg(5, 0x1332)
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252 sl.write_reg(6, 0x12345)
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253 assert sl.read_reg(3) == 0x1337
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254 assert sl.read_reg(5) == 0x1332
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255 assert sl.read_reg(6) == 0x12345
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256 regs = sl.read_all_regs()
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257 for i in range(len(regs)):
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258 print('R{0}=0x{1:X}'.format(i, regs[i]))
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259
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260 sl.exitDebugMode()
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261 print('mode at end:', sl.CurrentModeString)
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262
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263 sl.close()
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264 print('Test succes!')
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265
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