--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/python/adi.py	Sat Feb 09 16:05:36 2013 +0100
@@ -0,0 +1,59 @@
+
+# Implementation of the ADI (ARM Debug Interface) v5 interface.
+
+COMPONENT_CLASSES = {0x1: 'ROM table'}
+
+class Adi:
+   def __init__(self, iface):
+      self.iface = iface
+   def r32(self, address):
+      return self.iface.read_debug32(address)
+   def w32(self, address, value):
+      self.iface.write_debug32(address, value)
+   def getId(self, offset):
+      print('reading id from {0:X}'.format(offset))
+      pid4 = self.r32(offset + 0xFD0)
+      #print('pid4', pid4)
+      pid5 = self.r32(offset + 0xFD4)
+      pid6 = self.r32(offset + 0xFD8)
+      pid7 = self.r32(offset + 0xFDC)
+      pid0 = self.r32(offset + 0xFE0)
+      pid1 = self.r32(offset + 0xFE4)
+      pid2 = self.r32(offset + 0xFE8)
+      pid3 = self.r32(offset + 0xFEC)
+      cid0 = self.r32(offset + 0xFF0)
+      cid1 = self.r32(offset + 0xFF4)
+      cid2 = self.r32(offset + 0xFF8)
+      cid3 = self.r32(offset + 0xFFC)
+      pids = [pid0, pid1, pid2, pid3, pid4, pid5, pid6, pid7]
+      cids = [cid0, cid1, cid2, cid3]
+      print('cids:', [hex(x) for x in cids], 'pids', [hex(x) for x in pids])
+      valid = cid0 == 0xD and (cid1 & 0xF) == 0x0 and cid2 == 0x5 and cid3 == 0xB1
+      if valid:
+         component_class = cid1 >> 4
+      else:
+         print('invalid class')
+         component_class = 0
+      # TODO: use pids
+      return component_class, pids
+      
+   def parseRomTable(self, offset):
+      assert (offset & 0xFFF) == 0
+      component_class, pid = self.getId(offset)
+      assert component_class == 1
+      print('Component class:', COMPONENT_CLASSES[component_class])
+      print('memory also on this bus:', self.r32(offset + 0xFCC))
+      idx = 0
+      entry = self.r32(offset + idx * 4)
+      while entry != 0:
+         #print('Entry: {0:X}'.format(entry))
+         entryOffset = entry & 0xFFFFF000
+         cls, pids = self.getId((offset + entryOffset) & 0xFFFFFFFF)
+         print('class:', cls)
+         if cls == 9:
+            print('Debug block found!')
+
+         idx += 1
+         entry = self.r32(offset + idx * 4)
+
+

--- a/python/st-util.py	Sun Jan 27 13:18:53 2013 +0100
+++ b/python/st-util.py	Sat Feb 09 16:05:36 2013 +0100
@@ -74,6 +74,8 @@
       self.mdl = RegisterModel()
       self.setModel(self.mdl)
    def refresh(self):
+      if self.mdl.device:
+         self.setEnabled(not self.mdl.device.Running)
       self.mdl.refresh()
 
 class MemoryView(QWidget):
@@ -136,16 +138,19 @@
       self.runAction = genAction('Run', self.doRun)
       self.stopAction = genAction('Stop', self.doHalt)
       self.resetAction = genAction('Reset', self.doReset)
+      self.enableTraceAction = genAction('Enable trace', self.doEnableTrace)
       self.updateEnables()
    def updateEnables(self):
       if self.device:
          self.resetAction.setEnabled(True)
+         self.enableTraceAction.setEnabled(True)
          self.runAction.setEnabled(not self.device.Running)
          self.stepAction.setEnabled(not self.device.Running)
          self.stopAction.setEnabled(self.device.Running)
          self.statusChange.emit()
       else:
          self.resetAction.setEnabled(False)
+         self.enableTraceAction.setEnabled(False)
          self.runAction.setEnabled(False)
          self.stepAction.setEnabled(False)
          self.stopAction.setEnabled(False)
@@ -161,6 +166,9 @@
    def doHalt(self):
       self.device.iface.halt()
       self.updateEnables()
+   def doEnableTrace(self):
+      self.device.iface.traceEnable()
+      self.updateEnables()
    def setDevice(self, dev):
       self.device = dev
       self.updateEnables()

--- a/python/stlink.py	Sun Jan 27 13:18:53 2013 +0100
+++ b/python/stlink.py	Sat Feb 09 16:05:36 2013 +0100
@@ -1,6 +1,7 @@
 import struct, time
 from usb import UsbContext, UsbDevice
 from devices import Interface, STLinkException, registerInterface
+import adi
 
 ST_VID, STLINK2_PID = 0x0483, 0x3748
 
@@ -172,6 +173,12 @@
       cmd[0:2] = DEBUG_COMMAND, DEBUG_FORCEDEBUG
       self.send_recv(cmd, 2)
 
+   def traceEnable(self):
+      DEMCR = 0xE000EDFC
+      v = self.read_debug32(DEMCR)
+      v |= (1 << 24)
+      self.write_debug32(DEMCR, v)
+
    # Helper 1 functions:
    def write_debug32(self, address, value):
       cmd = bytearray(16)
@@ -256,6 +263,47 @@
    regs = sl.read_all_regs()
    for i in range(len(regs)):
       print('R{0}=0x{1:X}'.format(i, regs[i]))
+   
+   # Test CoreSight registers:
+   idr4 = sl.read_debug32(0xE0041fd0)
+   print('idr4 =', idr4)
+
+   print('== ADI ==')
+   a = adi.Adi(sl)
+   a.parseRomTable(0xE00FF000) # why is rom table at 0xE00FF000?
+   print('== ADI ==')
+
+   # Detect ROM table:
+   id4 = sl.read_debug32(0xE00FFFD0)
+   id5 = sl.read_debug32(0xE00FFFD4)
+   id6 = sl.read_debug32(0xE00FFFD8)
+   id7 = sl.read_debug32(0xE00FFFDC)
+   id0 = sl.read_debug32(0xE00FFFE0)
+   id1 = sl.read_debug32(0xE00FFFE4)
+   id2 = sl.read_debug32(0xE00FFFE8)
+   id3 = sl.read_debug32(0xE00FFFEC)
+   pIDs = [id0, id1, id2, id3, id4, id5, id6, id7]
+   print(pIDs)
+
+   print('reading from 0xE00FF000')
+   scs = sl.read_debug32(0xE00FF000)
+   print('scs {0:08X}'.format(scs))
+   dwt = sl.read_debug32(0xE00FF004)
+   print('dwt {0:08X}'.format(dwt))
+   fpb = sl.read_debug32(0xE00FF008)
+   print('fpb {0:08X}'.format(fpb))
+   itm = sl.read_debug32(0xE00FF00C)
+   print('itm {0:08X}'.format(itm))
+   tpiu = sl.read_debug32(0xE00FF010)
+   print('tpiu {0:08X}'.format(tpiu))
+   etm = sl.read_debug32(0xE00FF014)
+   print('etm {0:08X}'.format(etm))
+   assert sl.read_debug32(0xE00FF018) == 0x0 # end marker
+
+   devid = sl.read_debug32(0xE0040FC8)
+   print('TPIU_DEVID: {0:X}'.format(devid))
+   devtype = sl.read_debug32(0xE0040FCC)
+   print('TPIU_TYPEID: {0:X}'.format(devtype))
 
    sl.exitDebugMode()
    print('mode at end:', sl.CurrentModeString)