--- a/python/stlink.py	Sat Jan 12 12:52:18 2013 +0100
+++ b/python/stlink.py	Sat Jan 12 15:43:10 2013 +0100
@@ -29,6 +29,7 @@
 DEBUG_ENTER_SWD = 0xa3
 DEBUG_GETSTATUS = 0x01
 DEBUG_RESETSYS = 0x03
+DEBUG_READALLREGS = 0x04
 DEBUG_READREG = 0x5
 DEBUG_WRITEREG = 0x6
 DEBUG_READMEM_32BIT = 0x7
@@ -104,6 +105,7 @@
          if len(stlink2s) > 1:
             print('More then one stlink2 found, picking first one')
          stlink2 = stlink2s[0]
+      assert checkDevice(stlink2)
       self.stlink2 = stlink2
    def open(self):
       self.devHandle = self.stlink2.open()
@@ -395,6 +397,12 @@
       cmd[0:3] = DEBUG_COMMAND, DEBUG_READREG, reg
       reply = self.send_recv(cmd, 4)
       return struct.unpack('<I', reply)[0]
+   def read_all_regs(self):
+      cmd = bytearray(16)
+      cmd[0:2] = DEBUG_COMMAND, DEBUG_READALLREGS
+      reply = self.send_recv(cmd, 84)
+      fmt = '<' + 'I' * 21 # unpack 21 register values
+      return list(struct.unpack(fmt, reply))
    def write_mem32(self, address, content):
       assert len(content) % 4 == 0
       cmd = bytearray(16)
@@ -443,12 +451,18 @@
    print('status: {0}'.format(sl.StatusString))
 
    # test registers:
+   sl.write_reg(0, 0xdeadbeef)
+   sl.write_reg(1, 0xcafebabe)
+   sl.write_reg(2, 0xc0ffee)
    sl.write_reg(3, 0x1337)
-   sl.write_reg(2, 0x1332)
+   sl.write_reg(5, 0x1332)
    sl.write_reg(6, 0x12345)
    assert sl.read_reg(3) == 0x1337
-   assert sl.read_reg(2) == 0x1332
+   assert sl.read_reg(5) == 0x1332
    assert sl.read_reg(6) == 0x12345
+   regs = sl.read_all_regs()
+   for i in range(len(regs)):
+      print('R{0}=0x{1:X}'.format(i, regs[i]))
 
    sl.exitDebugMode()
    print('mode at end:', sl.CurrentModeString)