Mercurial > lcfOS
annotate python/cortexm3.py @ 267:e7c8f7eb3f59
Added tag Working chain 1 for changeset 649884d9dc61
| author | Windel Bouwman |
|---|---|
| date | Mon, 12 Aug 2013 20:14:47 +0200 |
| parents | ed14e077124c |
| children | 5ec7580976d9 |
| rev | line source |
|---|---|
| 261 | 1 import struct |
| 2 import types | |
| 235 | 3 from target import Register, Instruction, Target, Imm8, Label, Imm3, LabelRef, Imm32 |
| 234 | 4 from asmnodes import ASymbol, ANumber, AUnop, ABinop |
| 202 | 5 from ppci import CompilerError |
| 205 | 6 import ir |
| 202 | 7 |
| 218 | 8 # TODO: encode this in DSL (domain specific language) |
| 9 | |
| 202 | 10 def u16(h): |
| 11 return struct.pack('<H', h) | |
| 12 | |
| 205 | 13 def u32(x): |
| 14 return struct.pack('<I', x) | |
| 15 | |
| 202 | 16 armtarget = Target('arm') |
| 17 | |
| 18 class ArmReg(Register): | |
| 19 def __init__(self, num, name): | |
| 20 super().__init__(name) | |
| 21 self.num = num | |
| 206 | 22 def __repr__(self): |
| 23 return self.name | |
| 202 | 24 |
| 203 | 25 class RegOp: |
| 26 def __init__(self, num): | |
| 206 | 27 assert num < 16 |
| 203 | 28 self.num = num |
| 29 | |
| 30 @classmethod | |
| 31 def Create(cls, vop): | |
| 32 if type(vop) is ASymbol: | |
| 33 name = vop.name | |
| 34 regs = {} | |
| 35 for r in armtarget.registers: | |
| 36 regs[r.name] = r | |
| 37 if name in regs: | |
| 38 r = regs[name] | |
| 39 return cls(r.num) | |
| 234 | 40 |
| 219 | 41 class Reg8Op: |
| 42 def __init__(self, num): | |
| 43 assert num < 8 | |
| 44 self.num = num | |
| 45 | |
| 46 @classmethod | |
| 47 def Create(cls, vop): | |
| 48 if type(vop) is ASymbol: | |
| 49 name = vop.name | |
| 50 regs = {} | |
| 51 for r in armtarget.registers: | |
| 52 regs[r.name] = r | |
| 53 if name in regs: | |
| 54 r = regs[name] | |
| 55 if r.num < 8: | |
| 56 return cls(r.num) | |
| 203 | 57 |
| 206 | 58 def getRegNum(n): |
| 59 for r in armtarget.registers: | |
| 60 if r.num == n: | |
| 61 return r | |
| 203 | 62 |
| 206 | 63 def getRegisterRange(n1, n2): |
| 64 regs = [] | |
| 65 if n1.num < n2.num: | |
| 66 for n in range(n1.num, n2.num + 1): | |
| 67 r = getRegNum(n) | |
| 68 assert r | |
| 69 regs.append(r) | |
| 70 return regs | |
| 203 | 71 |
| 224 | 72 def isRegOffset(regname, x, y): |
| 73 if type(x) is ASymbol and type(y) is ANumber and x.name.upper() == regname: | |
| 74 return y.number | |
| 75 elif type(y) is ASymbol and type(x) is ANumber and y.name.upper() == regname: | |
| 76 return x.number | |
| 77 | |
| 78 | |
| 79 class MemRegXRel: | |
| 80 def __init__(self, offset): | |
| 81 assert offset % 4 == 0 | |
| 212 | 82 self.offset = offset |
| 83 | |
| 219 | 84 def __repr__(self): |
| 224 | 85 return '[{}, #{}]'.format(self.regname, self.offset) |
| 219 | 86 |
| 212 | 87 @classmethod |
| 88 def Create(cls, vop): | |
| 89 if type(vop) is AUnop and vop.operation == '[]': | |
| 90 vop = vop.arg # descent | |
| 224 | 91 offset = isRegOffset(cls.regname, vop.arg1, vop.arg2) |
| 92 if type(offset) is int: | |
| 93 if offset % 4 == 0: | |
| 223 | 94 offset = vop.arg2.number |
| 95 return cls(offset) | |
| 224 | 96 elif type(vop) is ASymbol and vop.name.upper() == self.regname: |
| 223 | 97 return cls(0) |
| 98 | |
| 224 | 99 class MemSpRel(MemRegXRel): |
| 100 regname = 'SP' | |
| 101 | |
| 102 class MemPcRel(MemRegXRel): | |
| 103 regname = 'PC' | |
| 104 | |
| 225 | 105 class MemR8Rel: |
| 219 | 106 def __init__(self, basereg, offset): |
| 107 assert type(basereg) is ArmReg | |
| 108 self.basereg = basereg | |
| 109 self.offset = offset | |
| 110 | |
| 111 def __repr__(self): | |
| 112 return '[{}, #{}]'.format(self.basereg, self.offset) | |
| 113 | |
| 114 @classmethod | |
| 115 def Create(cls, vop): | |
| 116 if type(vop) is AUnop and vop.operation == '[]': | |
| 117 vop = vop.arg # descent | |
| 118 if type(vop) is ABinop: | |
| 119 if vop.op == '+' and type(vop.arg1) is ASymbol and type(vop.arg2) is ANumber: | |
| 120 offset = vop.arg2.number | |
| 121 if offset > 120: | |
| 122 return | |
| 123 basereg = Reg8Op.Create(vop.arg1) | |
| 124 if not basereg: | |
| 125 return | |
| 126 else: | |
| 127 return | |
| 128 elif type(vop) is ASymbol: | |
| 129 offset = 0 | |
| 130 basereg = Reg8Op.Create(vop) | |
| 131 if not basereg: | |
| 132 return | |
| 133 else: | |
| 134 return | |
| 135 return cls(getRegNum(basereg.num), offset) | |
| 212 | 136 |
| 205 | 137 class RegisterSet: |
| 138 def __init__(self, regs): | |
| 206 | 139 assert type(regs) is set |
| 140 self.regs = regs | |
| 141 def __repr__(self): | |
| 142 return ','.join([str(r) for r in self.regs]) | |
| 143 @classmethod | |
| 144 def Create(cls, vop): | |
| 145 assert type(vop) is AUnop and vop.operation == '{}' | |
| 146 assert type(vop.arg) is list | |
| 147 regs = set() | |
| 148 for arg in vop.arg: | |
| 149 if type(arg) is ASymbol: | |
| 150 reg = RegOp.Create(arg) | |
| 151 if not reg: | |
| 152 return | |
| 153 regs.add(reg) | |
| 154 elif type(arg) is ABinop and arg.op == '-': | |
| 155 reg1 = RegOp.Create(arg.arg1) | |
| 156 reg2 = RegOp.Create(arg.arg2) | |
| 157 if not reg1: | |
| 158 return | |
| 159 if not reg2: | |
| 160 return | |
| 161 for r in getRegisterRange(reg1, reg2): | |
| 162 regs.add(r) | |
| 163 else: | |
| 164 raise Exception('Cannot be') | |
| 165 return cls(regs) | |
| 166 | |
| 167 def registerNumbers(self): | |
| 168 return [r.num for r in self.regs] | |
| 205 | 169 |
| 202 | 170 # 8 bit registers: |
| 205 | 171 r0 = ArmReg(0, 'r0') |
| 172 armtarget.registers.append(r0) | |
| 206 | 173 r1 = ArmReg(1, 'r1') |
| 174 armtarget.registers.append(r1) | |
| 175 r2 = ArmReg(2, 'r2') | |
| 176 armtarget.registers.append(r2) | |
| 177 r3 = ArmReg(3, 'r3') | |
| 178 armtarget.registers.append(r3) | |
| 202 | 179 r4 = ArmReg(4, 'r4') |
| 180 armtarget.registers.append(r4) | |
| 203 | 181 r5 = ArmReg(5, 'r5') |
| 182 armtarget.registers.append(r5) | |
| 183 r6 = ArmReg(6, 'r6') | |
| 184 armtarget.registers.append(r6) | |
| 185 r7 = ArmReg(7, 'r7') | |
| 186 armtarget.registers.append(r7) | |
| 206 | 187 # Other registers: |
| 188 # TODO | |
| 189 sp = ArmReg(13, 'sp') | |
| 190 armtarget.registers.append(sp) | |
| 191 lr = ArmReg(14, 'lr') | |
| 192 armtarget.registers.append(lr) | |
| 193 pc = ArmReg(15, 'pc') | |
| 194 armtarget.registers.append(pc) | |
| 202 | 195 |
| 196 class ArmInstruction(Instruction): | |
| 197 pass | |
| 198 | |
| 235 | 199 |
| 200 @armtarget.instruction | |
| 205 | 201 class dcd_ins(ArmInstruction): |
| 202 mnemonic = 'dcd' | |
| 235 | 203 operands = (Imm32,) |
| 205 | 204 def __init__(self, expr): |
| 237 | 205 if isinstance(expr, Imm32): |
| 206 self.expr = expr.imm | |
| 207 self.label = None | |
| 208 elif isinstance(expr, LabelRef): | |
| 209 self.expr = 0 | |
| 210 self.label = expr | |
| 211 else: | |
| 212 raise NotImplementedError() | |
| 213 | |
| 214 def resolve(self, f): | |
| 215 if self.label: | |
| 216 self.expr = f(self.label.name) | |
| 219 | 217 |
| 205 | 218 def encode(self): |
| 219 return u32(self.expr) | |
| 202 | 220 |
| 219 | 221 def __repr__(self): |
| 222 return 'DCD 0x{0:X}'.format(self.expr) | |
| 223 | |
| 224 | |
| 225 | |
| 226 # Memory related | |
| 227 | |
| 228 class LS_imm5_base(ArmInstruction): | |
| 229 """ ??? Rt, [Rn, imm5] """ | |
| 225 | 230 operands = (Reg8Op, MemR8Rel) |
| 212 | 231 def __init__(self, rt, memop): |
| 232 assert memop.offset % 4 == 0 | |
| 233 self.imm5 = memop.offset >> 2 | |
| 234 self.rn = memop.basereg.num | |
| 225 | 235 self.rt = rt |
| 219 | 236 self.memloc = memop |
| 237 assert self.rn < 8 | |
| 225 | 238 assert self.rt.num < 8 |
| 212 | 239 |
| 240 def encode(self): | |
| 241 Rn = self.rn | |
| 225 | 242 Rt = self.rt.num |
| 212 | 243 imm5 = self.imm5 |
| 219 | 244 |
| 245 h = (self.opcode << 11) | (imm5 << 6) | (Rn << 3) | Rt | |
| 246 return u16(h) | |
| 247 def __repr__(self): | |
| 248 return '{} {}, {}'.format(self.mnemonic, self.rt, self.memloc) | |
| 249 | |
| 250 @armtarget.instruction | |
| 251 class storeimm5_ins(LS_imm5_base): | |
| 252 mnemonic = 'STR' | |
| 253 opcode = 0xC | |
| 254 | |
| 255 @armtarget.instruction | |
| 256 class loadimm5_ins(LS_imm5_base): | |
| 257 mnemonic = 'LDR' | |
| 258 opcode = 0xD | |
| 259 | |
| 260 class ls_sp_base_imm8(ArmInstruction): | |
| 224 | 261 operands = (Reg8Op, MemSpRel) |
| 219 | 262 def __init__(self, rt, memop): |
| 263 self.rt = rt | |
| 264 self.offset = memop.offset | |
| 265 | |
| 266 def encode(self): | |
| 267 rt = self.rt.num | |
| 268 assert rt < 8 | |
| 269 imm8 = self.offset >> 2 | |
| 270 assert imm8 < 256 | |
| 271 h = (self.opcode << 8) | (rt << 8) | imm8 | |
| 212 | 272 return u16(h) |
| 273 | |
| 219 | 274 def __repr__(self): |
| 275 return '{} {}, [sp,#{}]'.format(self.mnemonic, self.rt, self.offset) | |
| 276 | |
| 236 | 277 def align(x, m): |
| 278 while ((x % m) != 0): | |
| 279 x = x + 1 | |
| 280 return x | |
| 281 | |
| 212 | 282 @armtarget.instruction |
| 219 | 283 class ldr_pcrel(ArmInstruction): |
| 284 """ ldr Rt, [PC, imm8], store value into memory """ | |
| 212 | 285 mnemonic = 'ldr' |
| 235 | 286 operands = (RegOp, LabelRef) |
| 219 | 287 def __init__(self, rt, label): |
| 235 | 288 assert isinstance(label, LabelRef) |
| 219 | 289 self.rt = rt |
| 290 self.label = label | |
| 291 self.offset = 0 | |
| 212 | 292 |
| 234 | 293 def resolve(self, f): |
| 235 | 294 la = f(self.label.name) |
| 236 | 295 sa = align(self.address + 2, 4) |
| 296 self.offset = (la - sa) | |
| 235 | 297 if self.offset < 0: |
| 298 self.offset = 0 | |
| 234 | 299 |
| 212 | 300 def encode(self): |
| 219 | 301 rt = self.rt.num |
| 302 assert rt < 8 | |
| 303 imm8 = self.offset >> 2 | |
| 304 assert imm8 < 256 | |
| 235 | 305 assert imm8 >= 0 |
| 219 | 306 h = (0x9 << 11) | (rt << 8) | imm8 |
| 212 | 307 return u16(h) |
| 308 | |
| 219 | 309 def __repr__(self): |
| 232 | 310 return 'LDR {}, {}'.format(self.rt, self.label.name) |
| 219 | 311 |
| 312 @armtarget.instruction | |
| 313 class ldr_sprel(ls_sp_base_imm8): | |
| 314 """ ldr Rt, [SP, imm8] """ | |
| 315 mnemonic = 'LDR' | |
| 316 opcode = 0x98 | |
| 317 | |
| 318 @armtarget.instruction | |
| 319 class str_sprel(ls_sp_base_imm8): | |
| 320 """ str Rt, [SP, imm8] """ | |
| 321 mnemonic = 'STR' | |
| 322 opcode = 0x90 | |
| 323 | |
| 212 | 324 @armtarget.instruction |
| 202 | 325 class mov_ins(ArmInstruction): |
| 326 """ mov Rd, imm8, move immediate value into register """ | |
| 327 mnemonic = 'mov' | |
| 203 | 328 opcode = 4 # 00100 Rd(3) imm8 |
| 329 operands = (RegOp, Imm8) | |
| 205 | 330 irpattern = ir.ImmLoad |
| 203 | 331 def __init__(self, rd, imm): |
| 332 self.imm = imm.imm | |
| 333 self.r = rd.num | |
| 205 | 334 |
| 202 | 335 def encode(self): |
| 336 rd = self.r | |
| 337 opcode = self.opcode | |
| 338 imm8 = self.imm | |
| 339 h = (opcode << 11) | (rd << 8) | imm8 | |
| 340 return u16(h) | |
| 219 | 341 def __repr__(self): |
| 342 return 'MOV {0}, xx?'.format(self.r) | |
| 232 | 343 |
| 344 | |
| 203 | 345 |
| 219 | 346 |
| 347 | |
| 348 # Arithmatics: | |
| 349 | |
| 203 | 350 @armtarget.instruction |
| 351 class addregregimm3_ins(ArmInstruction): | |
| 352 """ add Rd, Rn, imm3 """ | |
| 353 mnemonic = 'add' | |
| 354 opcode = 3 # 00011 | |
| 355 operands = (RegOp, RegOp, Imm3) | |
| 205 | 356 irpattern = 3 |
| 203 | 357 def __init__(self, rd, rn, imm3): |
| 358 self.rd = rd | |
| 359 self.rn = rn | |
| 360 self.imm3 = imm3 | |
| 361 def encode(self): | |
| 362 rd = self.rd.num | |
| 363 rn = self.rn.num | |
| 364 imm3 = self.imm3.imm | |
| 365 opcode = self.opcode | |
| 366 h = (opcode << 11) | (1 << 10) | (imm3 << 6) | (rn << 3) | rd | |
| 367 return u16(h) | |
| 368 | |
| 219 | 369 class regregreg_base(ArmInstruction): |
| 370 """ ??? Rd, Rn, Rm """ | |
| 371 operands = (Reg8Op, Reg8Op, Reg8Op) | |
| 372 def __init__(self, rd, rn, rm): | |
| 373 self.rd = rd | |
| 374 self.rn = rn | |
| 375 self.rm = rm | |
| 376 def encode(self): | |
| 377 rd = self.rd.num | |
| 378 rn = self.rn.num | |
| 379 rm = self.rm.num | |
| 380 h = (self.opcode << 9) | (rm << 6) | (rn << 3) | rd | |
| 381 return u16(h) | |
| 382 def __repr__(self): | |
| 383 return '{} {}, {}, {}'.format(self.mnemonic, self.rd, self.rn, self.rm) | |
| 384 | |
| 385 @armtarget.instruction | |
| 386 class addregs_ins(regregreg_base): | |
| 387 mnemonic = 'ADD' | |
| 388 opcode = 0b0001100 | |
| 389 | |
| 390 @armtarget.instruction | |
| 391 class subregs_ins(regregreg_base): | |
| 392 mnemonic = 'SUB' | |
| 393 opcode = 0b0001101 | |
| 394 | |
| 395 class regreg_base(ArmInstruction): | |
| 396 """ ??? Rdn, Rm """ | |
| 397 operands = (Reg8Op, Reg8Op) | |
| 398 def __init__(self, rdn, rm): | |
| 399 self.rdn = rdn | |
| 400 self.rm = rm | |
| 401 def encode(self): | |
| 402 rdn = self.rdn.num | |
| 403 rm = self.rm.num | |
| 404 h = (self.opcode << 6) | (rm << 3) | rdn | |
| 405 return u16(h) | |
| 406 def __repr__(self): | |
| 407 return '{} {}, {}'.format(self.mnemonic, self.rdn, self.rm) | |
| 408 | |
| 409 @armtarget.instruction | |
| 258 | 410 class movregreg_ins(regreg_base): |
| 411 """ mov Rd, Rm """ | |
| 412 mnemonic = 'mov' | |
| 413 opcode = 0 | |
| 414 | |
| 415 @armtarget.instruction | |
| 219 | 416 class andregs_ins(regreg_base): |
| 417 mnemonic = 'AND' | |
| 418 opcode = 0b0100000000 | |
| 419 | |
| 420 @armtarget.instruction | |
| 421 class orrregs_ins(regreg_base): | |
| 422 mnemonic = 'ORR' | |
| 423 opcode = 0b0100001100 | |
| 424 | |
| 425 @armtarget.instruction | |
| 426 class cmp_ins(regreg_base): | |
| 427 mnemonic = 'CMP' | |
| 428 opcode = 0b0100001010 | |
| 429 | |
| 203 | 430 @armtarget.instruction |
| 232 | 431 class lslregs_ins(regreg_base): |
| 432 mnemonic = 'LSL' | |
| 433 opcode = 0b0100000010 | |
| 434 | |
| 435 @armtarget.instruction | |
| 203 | 436 class cmpregimm8_ins(ArmInstruction): |
| 437 """ cmp Rn, imm8 """ | |
| 438 mnemonic = 'cmp' | |
| 439 opcode = 5 # 00101 | |
| 440 operands = (RegOp, Imm8) | |
| 441 def __init__(self, rn, imm): | |
| 442 self.rn = rn | |
| 443 self.imm = imm | |
| 444 def encode(self): | |
| 445 rn = self.rn.num | |
| 446 imm = self.imm.imm | |
| 447 opcode = self.opcode | |
| 448 h = (opcode << 11) | (rn << 8) | imm | |
| 449 return u16(h) | |
| 202 | 450 |
| 219 | 451 # Jumping: |
| 218 | 452 |
| 238 | 453 def wrap_negative(x, bits): |
| 454 b = struct.unpack('<I', struct.pack('<i', x))[0] | |
| 455 mask = (1 << bits) - 1 | |
| 456 return b & mask | |
| 457 | |
| 237 | 458 class jumpBase_ins(ArmInstruction): |
| 459 operands = (LabelRef,) | |
| 205 | 460 def __init__(self, target_label): |
| 237 | 461 assert type(target_label) is LabelRef |
| 205 | 462 self.target = target_label |
| 237 | 463 self.offset = 0 |
| 464 | |
| 465 def resolve(self, f): | |
| 466 la = f(self.target.name) | |
| 238 | 467 sa = self.address + 4 |
| 237 | 468 self.offset = (la - sa) |
| 238 | 469 #if self.offset < 0: |
| 470 # # TODO: handle negative jump | |
| 471 # self.offset = 0 | |
| 237 | 472 |
| 219 | 473 def __repr__(self): |
| 237 | 474 return '{} {}'.format(self.mnemonic, self.target.name) |
| 219 | 475 |
| 476 @armtarget.instruction | |
| 237 | 477 class b_ins(jumpBase_ins): |
| 478 mnemonic = 'B' | |
| 479 def encode(self): | |
| 238 | 480 imm11 = wrap_negative(self.offset >> 1, 11) |
| 481 h = (0b11100 << 11) | imm11 # | 1 # 1 to enable thumb mode | |
| 237 | 482 return u16(h) |
| 483 | |
|
251
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484 @armtarget.instruction |
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485 class bl_ins(jumpBase_ins): |
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486 mnemonic = 'BL' |
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487 def encode(self): |
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488 imm32 = wrap_negative(self.offset >> 1, 32) |
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489 imm11 = imm32 & 0x7FF |
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490 imm10 = (imm32 >> 11) & 0x3FF |
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491 j1 = 1 # TODO: what do these mean? |
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492 j2 = 1 |
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493 s = (imm32 >> 24) & 0x1 |
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494 h1 = (0b11110 << 11) | (s << 10) | imm10 |
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495 h2 = (0b1101 << 12) | (j1 << 13) | (j2 << 11) | imm11 |
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496 return u16(h1) + u16(h2) |
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497 |
| 237 | 498 class cond_base_ins(jumpBase_ins): |
| 499 def encode(self): | |
| 238 | 500 imm8 = wrap_negative(self.offset >> 1, 8) |
| 237 | 501 h = (0b1101 << 12) | (self.cond << 8) | imm8 |
| 502 return u16(h) | |
| 503 | |
| 262 | 504 |
| 237 | 505 @armtarget.instruction |
| 506 class beq_ins(cond_base_ins): | |
| 219 | 507 mnemonic = 'beq' |
| 237 | 508 cond = 0 |
| 509 | |
| 262 | 510 |
| 237 | 511 @armtarget.instruction |
| 262 | 512 class bne_ins(cond_base_ins): |
| 237 | 513 mnemonic = 'bne' |
| 514 cond = 1 | |
| 205 | 515 |
| 262 | 516 |
| 517 @armtarget.instruction | |
| 518 class blt_ins(cond_base_ins): | |
| 519 mnemonic = 'blt' | |
| 520 cond = 0b1011 | |
| 521 | |
| 522 | |
| 523 @armtarget.instruction | |
| 524 class blt_ins(cond_base_ins): | |
| 525 mnemonic = 'bgt' | |
| 526 cond = 0b1100 | |
| 527 | |
| 528 | |
| 205 | 529 @armtarget.instruction |
| 530 class push_ins(ArmInstruction): | |
| 206 | 531 operands = (RegisterSet,) |
| 205 | 532 mnemonic = 'push' |
| 533 def __init__(self, regs): | |
| 206 | 534 assert (type(regs),) == self.operands, (type(regs),) |
| 205 | 535 self.regs = regs |
| 206 | 536 def __repr__(self): |
| 537 return '{0} {{{1}}}'.format(self.mnemonic, self.regs) | |
| 205 | 538 def encode(self): |
| 206 | 539 reg_list = 0 |
| 540 M = 0 | |
| 541 for n in self.regs.registerNumbers(): | |
| 542 if n < 8: | |
| 543 reg_list |= (1 << n) | |
| 544 elif n == 14: | |
| 545 M = 1 | |
| 546 else: | |
| 547 raise NotImplementedError('not implemented for this register') | |
| 548 h = (0x5a << 9) | (M << 8) | reg_list | |
| 549 return u16(h) | |
| 205 | 550 |
| 551 @armtarget.instruction | |
| 552 class pop_ins(ArmInstruction): | |
| 206 | 553 operands = (RegisterSet,) |
| 205 | 554 mnemonic = 'pop' |
| 555 def __init__(self, regs): | |
| 556 self.regs = regs | |
| 207 | 557 def __repr__(self): |
| 558 return '{0} {{{1}}}'.format(self.mnemonic, self.regs) | |
| 205 | 559 def encode(self): |
| 206 | 560 reg_list = 0 |
| 561 P = 0 | |
| 562 for n in self.regs.registerNumbers(): | |
| 563 if n < 8: | |
| 564 reg_list |= (1 << n) | |
| 565 elif n == 15: | |
| 566 P = 1 | |
| 567 else: | |
| 568 raise NotImplementedError('not implemented for this register') | |
| 569 h = (0x5E << 9) | (P << 8) | reg_list | |
| 570 return u16(h) | |
| 205 | 571 |
| 572 @armtarget.instruction | |
| 202 | 573 class yield_ins(ArmInstruction): |
| 574 operands = () | |
| 575 mnemonic = 'yield' | |
| 576 def encode(self): | |
| 577 return u16(0xbf10) | |
| 578 | |
| 206 | 579 armtarget.check() |
| 580 |