annotate python/cortexm3.py @ 252:c4370696ccc7

added optimize function
author Windel Bouwman
date Tue, 30 Jul 2013 17:57:46 +0200
parents 6ed3d3a82a63
children 04c19282a5aa
rev   line source
205
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
1 import struct, types
235
ff40407c0240 Fix ALabel to Label
Windel Bouwman
parents: 234
diff changeset
2 from target import Register, Instruction, Target, Imm8, Label, Imm3, LabelRef, Imm32
234
Windel Bouwman
parents: 232
diff changeset
3 from asmnodes import ASymbol, ANumber, AUnop, ABinop
202
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
4 from ppci import CompilerError
205
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
5 import ir
202
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
6
218
494828a7adf1 added some sort of cache to assembler
Windel Bouwman
parents: 216
diff changeset
7 # TODO: encode this in DSL (domain specific language)
494828a7adf1 added some sort of cache to assembler
Windel Bouwman
parents: 216
diff changeset
8
202
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
9 def u16(h):
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
10 return struct.pack('<H', h)
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
11
205
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
12 def u32(x):
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
13 return struct.pack('<I', x)
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
14
202
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
15 armtarget = Target('arm')
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
16
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
17 class ArmReg(Register):
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
18 def __init__(self, num, name):
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
19 super().__init__(name)
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
20 self.num = num
206
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
21 def __repr__(self):
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
22 return self.name
202
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
23
203
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
24 class RegOp:
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
25 def __init__(self, num):
206
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
26 assert num < 16
203
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
27 self.num = num
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
28
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
29 @classmethod
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
30 def Create(cls, vop):
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
31 if type(vop) is ASymbol:
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
32 name = vop.name
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
33 regs = {}
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
34 for r in armtarget.registers:
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
35 regs[r.name] = r
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
36 if name in regs:
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
37 r = regs[name]
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
38 return cls(r.num)
234
Windel Bouwman
parents: 232
diff changeset
39
219
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
40 class Reg8Op:
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
41 def __init__(self, num):
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
42 assert num < 8
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
43 self.num = num
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
44
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
45 @classmethod
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
46 def Create(cls, vop):
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
47 if type(vop) is ASymbol:
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
48 name = vop.name
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
49 regs = {}
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
50 for r in armtarget.registers:
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
51 regs[r.name] = r
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
52 if name in regs:
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
53 r = regs[name]
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
54 if r.num < 8:
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
55 return cls(r.num)
203
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
56
206
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
57 def getRegNum(n):
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
58 for r in armtarget.registers:
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
59 if r.num == n:
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
60 return r
203
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
61
206
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
62 def getRegisterRange(n1, n2):
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
63 regs = []
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
64 if n1.num < n2.num:
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
65 for n in range(n1.num, n2.num + 1):
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
66 r = getRegNum(n)
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
67 assert r
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
68 regs.append(r)
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
69 return regs
203
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
70
224
5af52987f5bd Fixup of pc rel operand
Windel Bouwman
parents: 223
diff changeset
71 def isRegOffset(regname, x, y):
5af52987f5bd Fixup of pc rel operand
Windel Bouwman
parents: 223
diff changeset
72 if type(x) is ASymbol and type(y) is ANumber and x.name.upper() == regname:
5af52987f5bd Fixup of pc rel operand
Windel Bouwman
parents: 223
diff changeset
73 return y.number
5af52987f5bd Fixup of pc rel operand
Windel Bouwman
parents: 223
diff changeset
74 elif type(y) is ASymbol and type(x) is ANumber and y.name.upper() == regname:
5af52987f5bd Fixup of pc rel operand
Windel Bouwman
parents: 223
diff changeset
75 return x.number
5af52987f5bd Fixup of pc rel operand
Windel Bouwman
parents: 223
diff changeset
76
5af52987f5bd Fixup of pc rel operand
Windel Bouwman
parents: 223
diff changeset
77
5af52987f5bd Fixup of pc rel operand
Windel Bouwman
parents: 223
diff changeset
78 class MemRegXRel:
5af52987f5bd Fixup of pc rel operand
Windel Bouwman
parents: 223
diff changeset
79 def __init__(self, offset):
5af52987f5bd Fixup of pc rel operand
Windel Bouwman
parents: 223
diff changeset
80 assert offset % 4 == 0
212
62386bcee1ba Added parser combinator lib
Windel Bouwman
parents: 207
diff changeset
81 self.offset = offset
62386bcee1ba Added parser combinator lib
Windel Bouwman
parents: 207
diff changeset
82
219
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
83 def __repr__(self):
224
5af52987f5bd Fixup of pc rel operand
Windel Bouwman
parents: 223
diff changeset
84 return '[{}, #{}]'.format(self.regname, self.offset)
219
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
85
212
62386bcee1ba Added parser combinator lib
Windel Bouwman
parents: 207
diff changeset
86 @classmethod
62386bcee1ba Added parser combinator lib
Windel Bouwman
parents: 207
diff changeset
87 def Create(cls, vop):
62386bcee1ba Added parser combinator lib
Windel Bouwman
parents: 207
diff changeset
88 if type(vop) is AUnop and vop.operation == '[]':
62386bcee1ba Added parser combinator lib
Windel Bouwman
parents: 207
diff changeset
89 vop = vop.arg # descent
224
5af52987f5bd Fixup of pc rel operand
Windel Bouwman
parents: 223
diff changeset
90 offset = isRegOffset(cls.regname, vop.arg1, vop.arg2)
5af52987f5bd Fixup of pc rel operand
Windel Bouwman
parents: 223
diff changeset
91 if type(offset) is int:
5af52987f5bd Fixup of pc rel operand
Windel Bouwman
parents: 223
diff changeset
92 if offset % 4 == 0:
223
85c8105318e7 Fixup of parser
Windel Bouwman
parents: 219
diff changeset
93 offset = vop.arg2.number
85c8105318e7 Fixup of parser
Windel Bouwman
parents: 219
diff changeset
94 return cls(offset)
224
5af52987f5bd Fixup of pc rel operand
Windel Bouwman
parents: 223
diff changeset
95 elif type(vop) is ASymbol and vop.name.upper() == self.regname:
223
85c8105318e7 Fixup of parser
Windel Bouwman
parents: 219
diff changeset
96 return cls(0)
85c8105318e7 Fixup of parser
Windel Bouwman
parents: 219
diff changeset
97
224
5af52987f5bd Fixup of pc rel operand
Windel Bouwman
parents: 223
diff changeset
98 class MemSpRel(MemRegXRel):
5af52987f5bd Fixup of pc rel operand
Windel Bouwman
parents: 223
diff changeset
99 regname = 'SP'
5af52987f5bd Fixup of pc rel operand
Windel Bouwman
parents: 223
diff changeset
100
5af52987f5bd Fixup of pc rel operand
Windel Bouwman
parents: 223
diff changeset
101 class MemPcRel(MemRegXRel):
5af52987f5bd Fixup of pc rel operand
Windel Bouwman
parents: 223
diff changeset
102 regname = 'PC'
5af52987f5bd Fixup of pc rel operand
Windel Bouwman
parents: 223
diff changeset
103
225
1c7364bd74c7 Fixed pointer deref
Windel Bouwman
parents: 224
diff changeset
104 class MemR8Rel:
219
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
105 def __init__(self, basereg, offset):
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
106 assert type(basereg) is ArmReg
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
107 self.basereg = basereg
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
108 self.offset = offset
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
109
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
110 def __repr__(self):
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
111 return '[{}, #{}]'.format(self.basereg, self.offset)
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
112
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
113 @classmethod
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
114 def Create(cls, vop):
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
115 if type(vop) is AUnop and vop.operation == '[]':
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
116 vop = vop.arg # descent
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
117 if type(vop) is ABinop:
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
118 if vop.op == '+' and type(vop.arg1) is ASymbol and type(vop.arg2) is ANumber:
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
119 offset = vop.arg2.number
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
120 if offset > 120:
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
121 return
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
122 basereg = Reg8Op.Create(vop.arg1)
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
123 if not basereg:
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
124 return
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
125 else:
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
126 return
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
127 elif type(vop) is ASymbol:
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
128 offset = 0
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
129 basereg = Reg8Op.Create(vop)
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
130 if not basereg:
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
131 return
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
132 else:
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
133 return
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
134 return cls(getRegNum(basereg.num), offset)
212
62386bcee1ba Added parser combinator lib
Windel Bouwman
parents: 207
diff changeset
135
205
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
136 class RegisterSet:
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
137 def __init__(self, regs):
206
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
138 assert type(regs) is set
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
139 self.regs = regs
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
140 def __repr__(self):
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
141 return ','.join([str(r) for r in self.regs])
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
142 @classmethod
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
143 def Create(cls, vop):
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
144 assert type(vop) is AUnop and vop.operation == '{}'
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
145 assert type(vop.arg) is list
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
146 regs = set()
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
147 for arg in vop.arg:
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
148 if type(arg) is ASymbol:
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
149 reg = RegOp.Create(arg)
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
150 if not reg:
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
151 return
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
152 regs.add(reg)
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
153 elif type(arg) is ABinop and arg.op == '-':
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
154 reg1 = RegOp.Create(arg.arg1)
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
155 reg2 = RegOp.Create(arg.arg2)
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
156 if not reg1:
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
157 return
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
158 if not reg2:
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
159 return
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
160 for r in getRegisterRange(reg1, reg2):
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
161 regs.add(r)
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
162 else:
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
163 raise Exception('Cannot be')
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
164 return cls(regs)
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
165
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
166 def registerNumbers(self):
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
167 return [r.num for r in self.regs]
205
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
168
202
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
169 # 8 bit registers:
205
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
170 r0 = ArmReg(0, 'r0')
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
171 armtarget.registers.append(r0)
206
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
172 r1 = ArmReg(1, 'r1')
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
173 armtarget.registers.append(r1)
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
174 r2 = ArmReg(2, 'r2')
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
175 armtarget.registers.append(r2)
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
176 r3 = ArmReg(3, 'r3')
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
177 armtarget.registers.append(r3)
202
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
178 r4 = ArmReg(4, 'r4')
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
179 armtarget.registers.append(r4)
203
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
180 r5 = ArmReg(5, 'r5')
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
181 armtarget.registers.append(r5)
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
182 r6 = ArmReg(6, 'r6')
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
183 armtarget.registers.append(r6)
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
184 r7 = ArmReg(7, 'r7')
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
185 armtarget.registers.append(r7)
206
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
186 # Other registers:
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
187 # TODO
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
188 sp = ArmReg(13, 'sp')
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
189 armtarget.registers.append(sp)
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
190 lr = ArmReg(14, 'lr')
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
191 armtarget.registers.append(lr)
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
192 pc = ArmReg(15, 'pc')
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
193 armtarget.registers.append(pc)
202
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
194
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
195 class ArmInstruction(Instruction):
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
196 pass
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
197
235
ff40407c0240 Fix ALabel to Label
Windel Bouwman
parents: 234
diff changeset
198
ff40407c0240 Fix ALabel to Label
Windel Bouwman
parents: 234
diff changeset
199 @armtarget.instruction
205
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
200 class dcd_ins(ArmInstruction):
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
201 mnemonic = 'dcd'
235
ff40407c0240 Fix ALabel to Label
Windel Bouwman
parents: 234
diff changeset
202 operands = (Imm32,)
205
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
203 def __init__(self, expr):
237
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
204 if isinstance(expr, Imm32):
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
205 self.expr = expr.imm
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
206 self.label = None
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
207 elif isinstance(expr, LabelRef):
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
208 self.expr = 0
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
209 self.label = expr
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
210 else:
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
211 raise NotImplementedError()
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
212
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
213 def resolve(self, f):
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
214 if self.label:
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
215 self.expr = f(self.label.name)
219
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
216
205
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
217 def encode(self):
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
218 return u32(self.expr)
202
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
219
219
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
220 def __repr__(self):
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
221 return 'DCD 0x{0:X}'.format(self.expr)
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
222
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
223
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
224
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
225 # Memory related
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
226
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
227 class LS_imm5_base(ArmInstruction):
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
228 """ ??? Rt, [Rn, imm5] """
225
1c7364bd74c7 Fixed pointer deref
Windel Bouwman
parents: 224
diff changeset
229 operands = (Reg8Op, MemR8Rel)
212
62386bcee1ba Added parser combinator lib
Windel Bouwman
parents: 207
diff changeset
230 def __init__(self, rt, memop):
62386bcee1ba Added parser combinator lib
Windel Bouwman
parents: 207
diff changeset
231 assert memop.offset % 4 == 0
62386bcee1ba Added parser combinator lib
Windel Bouwman
parents: 207
diff changeset
232 self.imm5 = memop.offset >> 2
62386bcee1ba Added parser combinator lib
Windel Bouwman
parents: 207
diff changeset
233 self.rn = memop.basereg.num
225
1c7364bd74c7 Fixed pointer deref
Windel Bouwman
parents: 224
diff changeset
234 self.rt = rt
219
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
235 self.memloc = memop
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
236 assert self.rn < 8
225
1c7364bd74c7 Fixed pointer deref
Windel Bouwman
parents: 224
diff changeset
237 assert self.rt.num < 8
212
62386bcee1ba Added parser combinator lib
Windel Bouwman
parents: 207
diff changeset
238
62386bcee1ba Added parser combinator lib
Windel Bouwman
parents: 207
diff changeset
239 def encode(self):
62386bcee1ba Added parser combinator lib
Windel Bouwman
parents: 207
diff changeset
240 Rn = self.rn
225
1c7364bd74c7 Fixed pointer deref
Windel Bouwman
parents: 224
diff changeset
241 Rt = self.rt.num
212
62386bcee1ba Added parser combinator lib
Windel Bouwman
parents: 207
diff changeset
242 imm5 = self.imm5
219
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
243
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
244 h = (self.opcode << 11) | (imm5 << 6) | (Rn << 3) | Rt
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
245 return u16(h)
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
246 def __repr__(self):
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
247 return '{} {}, {}'.format(self.mnemonic, self.rt, self.memloc)
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
248
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
249 @armtarget.instruction
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
250 class storeimm5_ins(LS_imm5_base):
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
251 mnemonic = 'STR'
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
252 opcode = 0xC
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
253
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
254 @armtarget.instruction
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
255 class loadimm5_ins(LS_imm5_base):
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
256 mnemonic = 'LDR'
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
257 opcode = 0xD
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
258
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
259 class ls_sp_base_imm8(ArmInstruction):
224
5af52987f5bd Fixup of pc rel operand
Windel Bouwman
parents: 223
diff changeset
260 operands = (Reg8Op, MemSpRel)
219
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
261 def __init__(self, rt, memop):
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
262 self.rt = rt
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
263 self.offset = memop.offset
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
264
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
265 def encode(self):
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
266 rt = self.rt.num
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
267 assert rt < 8
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
268 imm8 = self.offset >> 2
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
269 assert imm8 < 256
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
270 h = (self.opcode << 8) | (rt << 8) | imm8
212
62386bcee1ba Added parser combinator lib
Windel Bouwman
parents: 207
diff changeset
271 return u16(h)
62386bcee1ba Added parser combinator lib
Windel Bouwman
parents: 207
diff changeset
272
219
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
273 def __repr__(self):
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
274 return '{} {}, [sp,#{}]'.format(self.mnemonic, self.rt, self.offset)
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
275
236
8786811a5a59 Fix pcrel
Windel Bouwman
parents: 235
diff changeset
276 def align(x, m):
8786811a5a59 Fix pcrel
Windel Bouwman
parents: 235
diff changeset
277 while ((x % m) != 0):
8786811a5a59 Fix pcrel
Windel Bouwman
parents: 235
diff changeset
278 x = x + 1
8786811a5a59 Fix pcrel
Windel Bouwman
parents: 235
diff changeset
279 return x
8786811a5a59 Fix pcrel
Windel Bouwman
parents: 235
diff changeset
280
212
62386bcee1ba Added parser combinator lib
Windel Bouwman
parents: 207
diff changeset
281 @armtarget.instruction
219
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
282 class ldr_pcrel(ArmInstruction):
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
283 """ ldr Rt, [PC, imm8], store value into memory """
212
62386bcee1ba Added parser combinator lib
Windel Bouwman
parents: 207
diff changeset
284 mnemonic = 'ldr'
235
ff40407c0240 Fix ALabel to Label
Windel Bouwman
parents: 234
diff changeset
285 operands = (RegOp, LabelRef)
219
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
286 def __init__(self, rt, label):
235
ff40407c0240 Fix ALabel to Label
Windel Bouwman
parents: 234
diff changeset
287 assert isinstance(label, LabelRef)
219
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
288 self.rt = rt
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
289 self.label = label
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
290 self.offset = 0
212
62386bcee1ba Added parser combinator lib
Windel Bouwman
parents: 207
diff changeset
291
234
Windel Bouwman
parents: 232
diff changeset
292 def resolve(self, f):
235
ff40407c0240 Fix ALabel to Label
Windel Bouwman
parents: 234
diff changeset
293 la = f(self.label.name)
236
8786811a5a59 Fix pcrel
Windel Bouwman
parents: 235
diff changeset
294 sa = align(self.address + 2, 4)
8786811a5a59 Fix pcrel
Windel Bouwman
parents: 235
diff changeset
295 self.offset = (la - sa)
235
ff40407c0240 Fix ALabel to Label
Windel Bouwman
parents: 234
diff changeset
296 if self.offset < 0:
ff40407c0240 Fix ALabel to Label
Windel Bouwman
parents: 234
diff changeset
297 self.offset = 0
234
Windel Bouwman
parents: 232
diff changeset
298
212
62386bcee1ba Added parser combinator lib
Windel Bouwman
parents: 207
diff changeset
299 def encode(self):
219
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
300 rt = self.rt.num
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
301 assert rt < 8
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
302 imm8 = self.offset >> 2
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
303 assert imm8 < 256
235
ff40407c0240 Fix ALabel to Label
Windel Bouwman
parents: 234
diff changeset
304 assert imm8 >= 0
219
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
305 h = (0x9 << 11) | (rt << 8) | imm8
212
62386bcee1ba Added parser combinator lib
Windel Bouwman
parents: 207
diff changeset
306 return u16(h)
62386bcee1ba Added parser combinator lib
Windel Bouwman
parents: 207
diff changeset
307
219
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
308 def __repr__(self):
232
e621e3ba78d2 Added left shift instruction
Windel Bouwman
parents: 225
diff changeset
309 return 'LDR {}, {}'.format(self.rt, self.label.name)
219
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
310
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
311 @armtarget.instruction
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
312 class ldr_sprel(ls_sp_base_imm8):
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
313 """ ldr Rt, [SP, imm8] """
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
314 mnemonic = 'LDR'
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
315 opcode = 0x98
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
316
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
317 @armtarget.instruction
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
318 class str_sprel(ls_sp_base_imm8):
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
319 """ str Rt, [SP, imm8] """
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
320 mnemonic = 'STR'
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
321 opcode = 0x90
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
322
212
62386bcee1ba Added parser combinator lib
Windel Bouwman
parents: 207
diff changeset
323 @armtarget.instruction
202
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
324 class mov_ins(ArmInstruction):
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
325 """ mov Rd, imm8, move immediate value into register """
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
326 mnemonic = 'mov'
203
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
327 opcode = 4 # 00100 Rd(3) imm8
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
328 operands = (RegOp, Imm8)
205
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
329 irpattern = ir.ImmLoad
203
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
330 def __init__(self, rd, imm):
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
331 self.imm = imm.imm
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
332 self.r = rd.num
205
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
333
202
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
334 def encode(self):
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
335 rd = self.r
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
336 opcode = self.opcode
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
337 imm8 = self.imm
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
338 h = (opcode << 11) | (rd << 8) | imm8
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
339 return u16(h)
219
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
340 def __repr__(self):
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
341 return 'MOV {0}, xx?'.format(self.r)
232
e621e3ba78d2 Added left shift instruction
Windel Bouwman
parents: 225
diff changeset
342
e621e3ba78d2 Added left shift instruction
Windel Bouwman
parents: 225
diff changeset
343
203
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
344 @armtarget.instruction
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
345 class movregreg_ins(ArmInstruction):
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
346 """ mov Rd, Rm """
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
347 mnemonic = 'mov'
238
90637d1bbfad Added test sequence 2
Windel Bouwman
parents: 237
diff changeset
348 operands = (Reg8Op, Reg8Op)
203
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
349 def __init__(self, rd, rm):
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
350 self.rd = rd
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
351 self.rm = rm
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
352 def encode(self):
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
353 rd = self.rd.num
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
354 rm = self.rm.num
238
90637d1bbfad Added test sequence 2
Windel Bouwman
parents: 237
diff changeset
355 h = 0 | (rm << 3) | rd
203
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
356 return u16(h)
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
357
219
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
358
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
359
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
360 # Arithmatics:
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
361
203
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
362 @armtarget.instruction
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
363 class addregregimm3_ins(ArmInstruction):
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
364 """ add Rd, Rn, imm3 """
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
365 mnemonic = 'add'
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
366 opcode = 3 # 00011
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
367 operands = (RegOp, RegOp, Imm3)
205
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
368 irpattern = 3
203
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
369 def __init__(self, rd, rn, imm3):
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
370 self.rd = rd
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
371 self.rn = rn
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
372 self.imm3 = imm3
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
373 def encode(self):
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
374 rd = self.rd.num
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
375 rn = self.rn.num
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
376 imm3 = self.imm3.imm
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
377 opcode = self.opcode
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
378 h = (opcode << 11) | (1 << 10) | (imm3 << 6) | (rn << 3) | rd
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
379 return u16(h)
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
380
219
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
381 class regregreg_base(ArmInstruction):
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
382 """ ??? Rd, Rn, Rm """
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
383 operands = (Reg8Op, Reg8Op, Reg8Op)
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
384 def __init__(self, rd, rn, rm):
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
385 self.rd = rd
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
386 self.rn = rn
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
387 self.rm = rm
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
388 def encode(self):
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
389 rd = self.rd.num
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
390 rn = self.rn.num
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
391 rm = self.rm.num
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
392 h = (self.opcode << 9) | (rm << 6) | (rn << 3) | rd
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
393 return u16(h)
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
394 def __repr__(self):
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
395 return '{} {}, {}, {}'.format(self.mnemonic, self.rd, self.rn, self.rm)
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
396
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
397 @armtarget.instruction
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
398 class addregs_ins(regregreg_base):
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
399 mnemonic = 'ADD'
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
400 opcode = 0b0001100
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
401
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
402 @armtarget.instruction
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
403 class subregs_ins(regregreg_base):
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
404 mnemonic = 'SUB'
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
405 opcode = 0b0001101
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
406
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
407 class regreg_base(ArmInstruction):
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
408 """ ??? Rdn, Rm """
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
409 operands = (Reg8Op, Reg8Op)
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
410 def __init__(self, rdn, rm):
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
411 self.rdn = rdn
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
412 self.rm = rm
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
413 def encode(self):
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
414 rdn = self.rdn.num
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
415 rm = self.rm.num
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
416 h = (self.opcode << 6) | (rm << 3) | rdn
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
417 return u16(h)
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
418 def __repr__(self):
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
419 return '{} {}, {}'.format(self.mnemonic, self.rdn, self.rm)
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
420
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
421 @armtarget.instruction
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
422 class andregs_ins(regreg_base):
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
423 mnemonic = 'AND'
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
424 opcode = 0b0100000000
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
425
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
426 @armtarget.instruction
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
427 class orrregs_ins(regreg_base):
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
428 mnemonic = 'ORR'
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
429 opcode = 0b0100001100
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
430
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
431 @armtarget.instruction
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
432 class cmp_ins(regreg_base):
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
433 mnemonic = 'CMP'
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
434 opcode = 0b0100001010
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
435
203
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
436 @armtarget.instruction
232
e621e3ba78d2 Added left shift instruction
Windel Bouwman
parents: 225
diff changeset
437 class lslregs_ins(regreg_base):
e621e3ba78d2 Added left shift instruction
Windel Bouwman
parents: 225
diff changeset
438 mnemonic = 'LSL'
e621e3ba78d2 Added left shift instruction
Windel Bouwman
parents: 225
diff changeset
439 opcode = 0b0100000010
e621e3ba78d2 Added left shift instruction
Windel Bouwman
parents: 225
diff changeset
440
e621e3ba78d2 Added left shift instruction
Windel Bouwman
parents: 225
diff changeset
441 @armtarget.instruction
203
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
442 class cmpregimm8_ins(ArmInstruction):
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
443 """ cmp Rn, imm8 """
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
444 mnemonic = 'cmp'
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
445 opcode = 5 # 00101
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
446 operands = (RegOp, Imm8)
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
447 def __init__(self, rn, imm):
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
448 self.rn = rn
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
449 self.imm = imm
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
450 def encode(self):
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
451 rn = self.rn.num
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
452 imm = self.imm.imm
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
453 opcode = self.opcode
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
454 h = (opcode << 11) | (rn << 8) | imm
ca1ea402f6a1 Added some arm instructions
Windel Bouwman
parents: 202
diff changeset
455 return u16(h)
202
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
456
219
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
457 # Jumping:
218
494828a7adf1 added some sort of cache to assembler
Windel Bouwman
parents: 216
diff changeset
458
238
90637d1bbfad Added test sequence 2
Windel Bouwman
parents: 237
diff changeset
459 def wrap_negative(x, bits):
90637d1bbfad Added test sequence 2
Windel Bouwman
parents: 237
diff changeset
460 b = struct.unpack('<I', struct.pack('<i', x))[0]
90637d1bbfad Added test sequence 2
Windel Bouwman
parents: 237
diff changeset
461 mask = (1 << bits) - 1
90637d1bbfad Added test sequence 2
Windel Bouwman
parents: 237
diff changeset
462 return b & mask
90637d1bbfad Added test sequence 2
Windel Bouwman
parents: 237
diff changeset
463
237
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
464 class jumpBase_ins(ArmInstruction):
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
465 operands = (LabelRef,)
205
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
466 def __init__(self, target_label):
237
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
467 assert type(target_label) is LabelRef
205
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
468 self.target = target_label
237
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
469 self.offset = 0
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
470
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
471 def resolve(self, f):
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
472 la = f(self.target.name)
238
90637d1bbfad Added test sequence 2
Windel Bouwman
parents: 237
diff changeset
473 sa = self.address + 4
237
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
474 self.offset = (la - sa)
238
90637d1bbfad Added test sequence 2
Windel Bouwman
parents: 237
diff changeset
475 #if self.offset < 0:
90637d1bbfad Added test sequence 2
Windel Bouwman
parents: 237
diff changeset
476 # # TODO: handle negative jump
90637d1bbfad Added test sequence 2
Windel Bouwman
parents: 237
diff changeset
477 # self.offset = 0
237
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
478
219
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
479 def __repr__(self):
237
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
480 return '{} {}'.format(self.mnemonic, self.target.name)
219
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
481
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
482 @armtarget.instruction
237
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
483 class b_ins(jumpBase_ins):
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
484 mnemonic = 'B'
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
485 def encode(self):
238
90637d1bbfad Added test sequence 2
Windel Bouwman
parents: 237
diff changeset
486 imm11 = wrap_negative(self.offset >> 1, 11)
90637d1bbfad Added test sequence 2
Windel Bouwman
parents: 237
diff changeset
487 h = (0b11100 << 11) | imm11 # | 1 # 1 to enable thumb mode
237
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
488 return u16(h)
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
489
251
6ed3d3a82a63 Added another c3 example. First import attempt
Windel Bouwman
parents: 238
diff changeset
490 @armtarget.instruction
6ed3d3a82a63 Added another c3 example. First import attempt
Windel Bouwman
parents: 238
diff changeset
491 class bl_ins(jumpBase_ins):
6ed3d3a82a63 Added another c3 example. First import attempt
Windel Bouwman
parents: 238
diff changeset
492 mnemonic = 'BL'
6ed3d3a82a63 Added another c3 example. First import attempt
Windel Bouwman
parents: 238
diff changeset
493 def encode(self):
6ed3d3a82a63 Added another c3 example. First import attempt
Windel Bouwman
parents: 238
diff changeset
494 imm32 = wrap_negative(self.offset >> 1, 32)
6ed3d3a82a63 Added another c3 example. First import attempt
Windel Bouwman
parents: 238
diff changeset
495 imm11 = imm32 & 0x7FF
6ed3d3a82a63 Added another c3 example. First import attempt
Windel Bouwman
parents: 238
diff changeset
496 imm10 = (imm32 >> 11) & 0x3FF
6ed3d3a82a63 Added another c3 example. First import attempt
Windel Bouwman
parents: 238
diff changeset
497 j1 = 1 # TODO: what do these mean?
6ed3d3a82a63 Added another c3 example. First import attempt
Windel Bouwman
parents: 238
diff changeset
498 j2 = 1
6ed3d3a82a63 Added another c3 example. First import attempt
Windel Bouwman
parents: 238
diff changeset
499 s = (imm32 >> 24) & 0x1
6ed3d3a82a63 Added another c3 example. First import attempt
Windel Bouwman
parents: 238
diff changeset
500 h1 = (0b11110 << 11) | (s << 10) | imm10
6ed3d3a82a63 Added another c3 example. First import attempt
Windel Bouwman
parents: 238
diff changeset
501 h2 = (0b1101 << 12) | (j1 << 13) | (j2 << 11) | imm11
6ed3d3a82a63 Added another c3 example. First import attempt
Windel Bouwman
parents: 238
diff changeset
502 return u16(h1) + u16(h2)
6ed3d3a82a63 Added another c3 example. First import attempt
Windel Bouwman
parents: 238
diff changeset
503
237
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
504 class cond_base_ins(jumpBase_ins):
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
505 def encode(self):
238
90637d1bbfad Added test sequence 2
Windel Bouwman
parents: 237
diff changeset
506 imm8 = wrap_negative(self.offset >> 1, 8)
237
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
507 h = (0b1101 << 12) | (self.cond << 8) | imm8
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
508 return u16(h)
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
509
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
510 @armtarget.instruction
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
511 class beq_ins(cond_base_ins):
219
1fa3e0050b49 Expanded ad hoc code generator
Windel Bouwman
parents: 218
diff changeset
512 mnemonic = 'beq'
237
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
513 cond = 0
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
514
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
515 @armtarget.instruction
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
516 class beq_ins(cond_base_ins):
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
517 mnemonic = 'bne'
81752b0f85a5 Added burn led test program
Windel Bouwman
parents: 236
diff changeset
518 cond = 1
205
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
519
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
520 @armtarget.instruction
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
521 class push_ins(ArmInstruction):
206
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
522 operands = (RegisterSet,)
205
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
523 mnemonic = 'push'
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
524 def __init__(self, regs):
206
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
525 assert (type(regs),) == self.operands, (type(regs),)
205
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
526 self.regs = regs
206
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
527 def __repr__(self):
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
528 return '{0} {{{1}}}'.format(self.mnemonic, self.regs)
205
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
529 def encode(self):
206
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
530 reg_list = 0
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
531 M = 0
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
532 for n in self.regs.registerNumbers():
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
533 if n < 8:
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
534 reg_list |= (1 << n)
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
535 elif n == 14:
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
536 M = 1
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
537 else:
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
538 raise NotImplementedError('not implemented for this register')
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
539 h = (0x5a << 9) | (M << 8) | reg_list
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
540 return u16(h)
205
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
541
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
542 @armtarget.instruction
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
543 class pop_ins(ArmInstruction):
206
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
544 operands = (RegisterSet,)
205
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
545 mnemonic = 'pop'
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
546 def __init__(self, regs):
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
547 self.regs = regs
207
8b2f20aae086 cleaning of files
Windel Bouwman
parents: 206
diff changeset
548 def __repr__(self):
8b2f20aae086 cleaning of files
Windel Bouwman
parents: 206
diff changeset
549 return '{0} {{{1}}}'.format(self.mnemonic, self.regs)
205
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
550 def encode(self):
206
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
551 reg_list = 0
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
552 P = 0
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
553 for n in self.regs.registerNumbers():
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
554 if n < 8:
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
555 reg_list |= (1 << n)
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
556 elif n == 15:
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
557 P = 1
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
558 else:
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
559 raise NotImplementedError('not implemented for this register')
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
560 h = (0x5E << 9) | (P << 8) | reg_list
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
561 return u16(h)
205
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
562
d77cb5962cc5 Added some handcoded arm code generation
Windel Bouwman
parents: 203
diff changeset
563 @armtarget.instruction
202
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
564 class yield_ins(ArmInstruction):
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
565 operands = ()
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
566 mnemonic = 'yield'
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
567 def encode(self):
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
568 return u16(0xbf10)
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
569
206
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
570 armtarget.check()
6c6bf8890d8a Added push and pop encodings
Windel Bouwman
parents: 205
diff changeset
571