Mercurial > lcfOS
annotate python/cortexm3.py @ 254:bd26dc13f270
Added logger
| author | Windel Bouwman |
|---|---|
| date | Wed, 31 Jul 2013 21:20:58 +0200 |
| parents | 6ed3d3a82a63 |
| children | 04c19282a5aa |
| rev | line source |
|---|---|
| 205 | 1 import struct, types |
| 235 | 2 from target import Register, Instruction, Target, Imm8, Label, Imm3, LabelRef, Imm32 |
| 234 | 3 from asmnodes import ASymbol, ANumber, AUnop, ABinop |
| 202 | 4 from ppci import CompilerError |
| 205 | 5 import ir |
| 202 | 6 |
| 218 | 7 # TODO: encode this in DSL (domain specific language) |
| 8 | |
| 202 | 9 def u16(h): |
| 10 return struct.pack('<H', h) | |
| 11 | |
| 205 | 12 def u32(x): |
| 13 return struct.pack('<I', x) | |
| 14 | |
| 202 | 15 armtarget = Target('arm') |
| 16 | |
| 17 class ArmReg(Register): | |
| 18 def __init__(self, num, name): | |
| 19 super().__init__(name) | |
| 20 self.num = num | |
| 206 | 21 def __repr__(self): |
| 22 return self.name | |
| 202 | 23 |
| 203 | 24 class RegOp: |
| 25 def __init__(self, num): | |
| 206 | 26 assert num < 16 |
| 203 | 27 self.num = num |
| 28 | |
| 29 @classmethod | |
| 30 def Create(cls, vop): | |
| 31 if type(vop) is ASymbol: | |
| 32 name = vop.name | |
| 33 regs = {} | |
| 34 for r in armtarget.registers: | |
| 35 regs[r.name] = r | |
| 36 if name in regs: | |
| 37 r = regs[name] | |
| 38 return cls(r.num) | |
| 234 | 39 |
| 219 | 40 class Reg8Op: |
| 41 def __init__(self, num): | |
| 42 assert num < 8 | |
| 43 self.num = num | |
| 44 | |
| 45 @classmethod | |
| 46 def Create(cls, vop): | |
| 47 if type(vop) is ASymbol: | |
| 48 name = vop.name | |
| 49 regs = {} | |
| 50 for r in armtarget.registers: | |
| 51 regs[r.name] = r | |
| 52 if name in regs: | |
| 53 r = regs[name] | |
| 54 if r.num < 8: | |
| 55 return cls(r.num) | |
| 203 | 56 |
| 206 | 57 def getRegNum(n): |
| 58 for r in armtarget.registers: | |
| 59 if r.num == n: | |
| 60 return r | |
| 203 | 61 |
| 206 | 62 def getRegisterRange(n1, n2): |
| 63 regs = [] | |
| 64 if n1.num < n2.num: | |
| 65 for n in range(n1.num, n2.num + 1): | |
| 66 r = getRegNum(n) | |
| 67 assert r | |
| 68 regs.append(r) | |
| 69 return regs | |
| 203 | 70 |
| 224 | 71 def isRegOffset(regname, x, y): |
| 72 if type(x) is ASymbol and type(y) is ANumber and x.name.upper() == regname: | |
| 73 return y.number | |
| 74 elif type(y) is ASymbol and type(x) is ANumber and y.name.upper() == regname: | |
| 75 return x.number | |
| 76 | |
| 77 | |
| 78 class MemRegXRel: | |
| 79 def __init__(self, offset): | |
| 80 assert offset % 4 == 0 | |
| 212 | 81 self.offset = offset |
| 82 | |
| 219 | 83 def __repr__(self): |
| 224 | 84 return '[{}, #{}]'.format(self.regname, self.offset) |
| 219 | 85 |
| 212 | 86 @classmethod |
| 87 def Create(cls, vop): | |
| 88 if type(vop) is AUnop and vop.operation == '[]': | |
| 89 vop = vop.arg # descent | |
| 224 | 90 offset = isRegOffset(cls.regname, vop.arg1, vop.arg2) |
| 91 if type(offset) is int: | |
| 92 if offset % 4 == 0: | |
| 223 | 93 offset = vop.arg2.number |
| 94 return cls(offset) | |
| 224 | 95 elif type(vop) is ASymbol and vop.name.upper() == self.regname: |
| 223 | 96 return cls(0) |
| 97 | |
| 224 | 98 class MemSpRel(MemRegXRel): |
| 99 regname = 'SP' | |
| 100 | |
| 101 class MemPcRel(MemRegXRel): | |
| 102 regname = 'PC' | |
| 103 | |
| 225 | 104 class MemR8Rel: |
| 219 | 105 def __init__(self, basereg, offset): |
| 106 assert type(basereg) is ArmReg | |
| 107 self.basereg = basereg | |
| 108 self.offset = offset | |
| 109 | |
| 110 def __repr__(self): | |
| 111 return '[{}, #{}]'.format(self.basereg, self.offset) | |
| 112 | |
| 113 @classmethod | |
| 114 def Create(cls, vop): | |
| 115 if type(vop) is AUnop and vop.operation == '[]': | |
| 116 vop = vop.arg # descent | |
| 117 if type(vop) is ABinop: | |
| 118 if vop.op == '+' and type(vop.arg1) is ASymbol and type(vop.arg2) is ANumber: | |
| 119 offset = vop.arg2.number | |
| 120 if offset > 120: | |
| 121 return | |
| 122 basereg = Reg8Op.Create(vop.arg1) | |
| 123 if not basereg: | |
| 124 return | |
| 125 else: | |
| 126 return | |
| 127 elif type(vop) is ASymbol: | |
| 128 offset = 0 | |
| 129 basereg = Reg8Op.Create(vop) | |
| 130 if not basereg: | |
| 131 return | |
| 132 else: | |
| 133 return | |
| 134 return cls(getRegNum(basereg.num), offset) | |
| 212 | 135 |
| 205 | 136 class RegisterSet: |
| 137 def __init__(self, regs): | |
| 206 | 138 assert type(regs) is set |
| 139 self.regs = regs | |
| 140 def __repr__(self): | |
| 141 return ','.join([str(r) for r in self.regs]) | |
| 142 @classmethod | |
| 143 def Create(cls, vop): | |
| 144 assert type(vop) is AUnop and vop.operation == '{}' | |
| 145 assert type(vop.arg) is list | |
| 146 regs = set() | |
| 147 for arg in vop.arg: | |
| 148 if type(arg) is ASymbol: | |
| 149 reg = RegOp.Create(arg) | |
| 150 if not reg: | |
| 151 return | |
| 152 regs.add(reg) | |
| 153 elif type(arg) is ABinop and arg.op == '-': | |
| 154 reg1 = RegOp.Create(arg.arg1) | |
| 155 reg2 = RegOp.Create(arg.arg2) | |
| 156 if not reg1: | |
| 157 return | |
| 158 if not reg2: | |
| 159 return | |
| 160 for r in getRegisterRange(reg1, reg2): | |
| 161 regs.add(r) | |
| 162 else: | |
| 163 raise Exception('Cannot be') | |
| 164 return cls(regs) | |
| 165 | |
| 166 def registerNumbers(self): | |
| 167 return [r.num for r in self.regs] | |
| 205 | 168 |
| 202 | 169 # 8 bit registers: |
| 205 | 170 r0 = ArmReg(0, 'r0') |
| 171 armtarget.registers.append(r0) | |
| 206 | 172 r1 = ArmReg(1, 'r1') |
| 173 armtarget.registers.append(r1) | |
| 174 r2 = ArmReg(2, 'r2') | |
| 175 armtarget.registers.append(r2) | |
| 176 r3 = ArmReg(3, 'r3') | |
| 177 armtarget.registers.append(r3) | |
| 202 | 178 r4 = ArmReg(4, 'r4') |
| 179 armtarget.registers.append(r4) | |
| 203 | 180 r5 = ArmReg(5, 'r5') |
| 181 armtarget.registers.append(r5) | |
| 182 r6 = ArmReg(6, 'r6') | |
| 183 armtarget.registers.append(r6) | |
| 184 r7 = ArmReg(7, 'r7') | |
| 185 armtarget.registers.append(r7) | |
| 206 | 186 # Other registers: |
| 187 # TODO | |
| 188 sp = ArmReg(13, 'sp') | |
| 189 armtarget.registers.append(sp) | |
| 190 lr = ArmReg(14, 'lr') | |
| 191 armtarget.registers.append(lr) | |
| 192 pc = ArmReg(15, 'pc') | |
| 193 armtarget.registers.append(pc) | |
| 202 | 194 |
| 195 class ArmInstruction(Instruction): | |
| 196 pass | |
| 197 | |
| 235 | 198 |
| 199 @armtarget.instruction | |
| 205 | 200 class dcd_ins(ArmInstruction): |
| 201 mnemonic = 'dcd' | |
| 235 | 202 operands = (Imm32,) |
| 205 | 203 def __init__(self, expr): |
| 237 | 204 if isinstance(expr, Imm32): |
| 205 self.expr = expr.imm | |
| 206 self.label = None | |
| 207 elif isinstance(expr, LabelRef): | |
| 208 self.expr = 0 | |
| 209 self.label = expr | |
| 210 else: | |
| 211 raise NotImplementedError() | |
| 212 | |
| 213 def resolve(self, f): | |
| 214 if self.label: | |
| 215 self.expr = f(self.label.name) | |
| 219 | 216 |
| 205 | 217 def encode(self): |
| 218 return u32(self.expr) | |
| 202 | 219 |
| 219 | 220 def __repr__(self): |
| 221 return 'DCD 0x{0:X}'.format(self.expr) | |
| 222 | |
| 223 | |
| 224 | |
| 225 # Memory related | |
| 226 | |
| 227 class LS_imm5_base(ArmInstruction): | |
| 228 """ ??? Rt, [Rn, imm5] """ | |
| 225 | 229 operands = (Reg8Op, MemR8Rel) |
| 212 | 230 def __init__(self, rt, memop): |
| 231 assert memop.offset % 4 == 0 | |
| 232 self.imm5 = memop.offset >> 2 | |
| 233 self.rn = memop.basereg.num | |
| 225 | 234 self.rt = rt |
| 219 | 235 self.memloc = memop |
| 236 assert self.rn < 8 | |
| 225 | 237 assert self.rt.num < 8 |
| 212 | 238 |
| 239 def encode(self): | |
| 240 Rn = self.rn | |
| 225 | 241 Rt = self.rt.num |
| 212 | 242 imm5 = self.imm5 |
| 219 | 243 |
| 244 h = (self.opcode << 11) | (imm5 << 6) | (Rn << 3) | Rt | |
| 245 return u16(h) | |
| 246 def __repr__(self): | |
| 247 return '{} {}, {}'.format(self.mnemonic, self.rt, self.memloc) | |
| 248 | |
| 249 @armtarget.instruction | |
| 250 class storeimm5_ins(LS_imm5_base): | |
| 251 mnemonic = 'STR' | |
| 252 opcode = 0xC | |
| 253 | |
| 254 @armtarget.instruction | |
| 255 class loadimm5_ins(LS_imm5_base): | |
| 256 mnemonic = 'LDR' | |
| 257 opcode = 0xD | |
| 258 | |
| 259 class ls_sp_base_imm8(ArmInstruction): | |
| 224 | 260 operands = (Reg8Op, MemSpRel) |
| 219 | 261 def __init__(self, rt, memop): |
| 262 self.rt = rt | |
| 263 self.offset = memop.offset | |
| 264 | |
| 265 def encode(self): | |
| 266 rt = self.rt.num | |
| 267 assert rt < 8 | |
| 268 imm8 = self.offset >> 2 | |
| 269 assert imm8 < 256 | |
| 270 h = (self.opcode << 8) | (rt << 8) | imm8 | |
| 212 | 271 return u16(h) |
| 272 | |
| 219 | 273 def __repr__(self): |
| 274 return '{} {}, [sp,#{}]'.format(self.mnemonic, self.rt, self.offset) | |
| 275 | |
| 236 | 276 def align(x, m): |
| 277 while ((x % m) != 0): | |
| 278 x = x + 1 | |
| 279 return x | |
| 280 | |
| 212 | 281 @armtarget.instruction |
| 219 | 282 class ldr_pcrel(ArmInstruction): |
| 283 """ ldr Rt, [PC, imm8], store value into memory """ | |
| 212 | 284 mnemonic = 'ldr' |
| 235 | 285 operands = (RegOp, LabelRef) |
| 219 | 286 def __init__(self, rt, label): |
| 235 | 287 assert isinstance(label, LabelRef) |
| 219 | 288 self.rt = rt |
| 289 self.label = label | |
| 290 self.offset = 0 | |
| 212 | 291 |
| 234 | 292 def resolve(self, f): |
| 235 | 293 la = f(self.label.name) |
| 236 | 294 sa = align(self.address + 2, 4) |
| 295 self.offset = (la - sa) | |
| 235 | 296 if self.offset < 0: |
| 297 self.offset = 0 | |
| 234 | 298 |
| 212 | 299 def encode(self): |
| 219 | 300 rt = self.rt.num |
| 301 assert rt < 8 | |
| 302 imm8 = self.offset >> 2 | |
| 303 assert imm8 < 256 | |
| 235 | 304 assert imm8 >= 0 |
| 219 | 305 h = (0x9 << 11) | (rt << 8) | imm8 |
| 212 | 306 return u16(h) |
| 307 | |
| 219 | 308 def __repr__(self): |
| 232 | 309 return 'LDR {}, {}'.format(self.rt, self.label.name) |
| 219 | 310 |
| 311 @armtarget.instruction | |
| 312 class ldr_sprel(ls_sp_base_imm8): | |
| 313 """ ldr Rt, [SP, imm8] """ | |
| 314 mnemonic = 'LDR' | |
| 315 opcode = 0x98 | |
| 316 | |
| 317 @armtarget.instruction | |
| 318 class str_sprel(ls_sp_base_imm8): | |
| 319 """ str Rt, [SP, imm8] """ | |
| 320 mnemonic = 'STR' | |
| 321 opcode = 0x90 | |
| 322 | |
| 212 | 323 @armtarget.instruction |
| 202 | 324 class mov_ins(ArmInstruction): |
| 325 """ mov Rd, imm8, move immediate value into register """ | |
| 326 mnemonic = 'mov' | |
| 203 | 327 opcode = 4 # 00100 Rd(3) imm8 |
| 328 operands = (RegOp, Imm8) | |
| 205 | 329 irpattern = ir.ImmLoad |
| 203 | 330 def __init__(self, rd, imm): |
| 331 self.imm = imm.imm | |
| 332 self.r = rd.num | |
| 205 | 333 |
| 202 | 334 def encode(self): |
| 335 rd = self.r | |
| 336 opcode = self.opcode | |
| 337 imm8 = self.imm | |
| 338 h = (opcode << 11) | (rd << 8) | imm8 | |
| 339 return u16(h) | |
| 219 | 340 def __repr__(self): |
| 341 return 'MOV {0}, xx?'.format(self.r) | |
| 232 | 342 |
| 343 | |
| 203 | 344 @armtarget.instruction |
| 345 class movregreg_ins(ArmInstruction): | |
| 346 """ mov Rd, Rm """ | |
| 347 mnemonic = 'mov' | |
| 238 | 348 operands = (Reg8Op, Reg8Op) |
| 203 | 349 def __init__(self, rd, rm): |
| 350 self.rd = rd | |
| 351 self.rm = rm | |
| 352 def encode(self): | |
| 353 rd = self.rd.num | |
| 354 rm = self.rm.num | |
| 238 | 355 h = 0 | (rm << 3) | rd |
| 203 | 356 return u16(h) |
| 357 | |
| 219 | 358 |
| 359 | |
| 360 # Arithmatics: | |
| 361 | |
| 203 | 362 @armtarget.instruction |
| 363 class addregregimm3_ins(ArmInstruction): | |
| 364 """ add Rd, Rn, imm3 """ | |
| 365 mnemonic = 'add' | |
| 366 opcode = 3 # 00011 | |
| 367 operands = (RegOp, RegOp, Imm3) | |
| 205 | 368 irpattern = 3 |
| 203 | 369 def __init__(self, rd, rn, imm3): |
| 370 self.rd = rd | |
| 371 self.rn = rn | |
| 372 self.imm3 = imm3 | |
| 373 def encode(self): | |
| 374 rd = self.rd.num | |
| 375 rn = self.rn.num | |
| 376 imm3 = self.imm3.imm | |
| 377 opcode = self.opcode | |
| 378 h = (opcode << 11) | (1 << 10) | (imm3 << 6) | (rn << 3) | rd | |
| 379 return u16(h) | |
| 380 | |
| 219 | 381 class regregreg_base(ArmInstruction): |
| 382 """ ??? Rd, Rn, Rm """ | |
| 383 operands = (Reg8Op, Reg8Op, Reg8Op) | |
| 384 def __init__(self, rd, rn, rm): | |
| 385 self.rd = rd | |
| 386 self.rn = rn | |
| 387 self.rm = rm | |
| 388 def encode(self): | |
| 389 rd = self.rd.num | |
| 390 rn = self.rn.num | |
| 391 rm = self.rm.num | |
| 392 h = (self.opcode << 9) | (rm << 6) | (rn << 3) | rd | |
| 393 return u16(h) | |
| 394 def __repr__(self): | |
| 395 return '{} {}, {}, {}'.format(self.mnemonic, self.rd, self.rn, self.rm) | |
| 396 | |
| 397 @armtarget.instruction | |
| 398 class addregs_ins(regregreg_base): | |
| 399 mnemonic = 'ADD' | |
| 400 opcode = 0b0001100 | |
| 401 | |
| 402 @armtarget.instruction | |
| 403 class subregs_ins(regregreg_base): | |
| 404 mnemonic = 'SUB' | |
| 405 opcode = 0b0001101 | |
| 406 | |
| 407 class regreg_base(ArmInstruction): | |
| 408 """ ??? Rdn, Rm """ | |
| 409 operands = (Reg8Op, Reg8Op) | |
| 410 def __init__(self, rdn, rm): | |
| 411 self.rdn = rdn | |
| 412 self.rm = rm | |
| 413 def encode(self): | |
| 414 rdn = self.rdn.num | |
| 415 rm = self.rm.num | |
| 416 h = (self.opcode << 6) | (rm << 3) | rdn | |
| 417 return u16(h) | |
| 418 def __repr__(self): | |
| 419 return '{} {}, {}'.format(self.mnemonic, self.rdn, self.rm) | |
| 420 | |
| 421 @armtarget.instruction | |
| 422 class andregs_ins(regreg_base): | |
| 423 mnemonic = 'AND' | |
| 424 opcode = 0b0100000000 | |
| 425 | |
| 426 @armtarget.instruction | |
| 427 class orrregs_ins(regreg_base): | |
| 428 mnemonic = 'ORR' | |
| 429 opcode = 0b0100001100 | |
| 430 | |
| 431 @armtarget.instruction | |
| 432 class cmp_ins(regreg_base): | |
| 433 mnemonic = 'CMP' | |
| 434 opcode = 0b0100001010 | |
| 435 | |
| 203 | 436 @armtarget.instruction |
| 232 | 437 class lslregs_ins(regreg_base): |
| 438 mnemonic = 'LSL' | |
| 439 opcode = 0b0100000010 | |
| 440 | |
| 441 @armtarget.instruction | |
| 203 | 442 class cmpregimm8_ins(ArmInstruction): |
| 443 """ cmp Rn, imm8 """ | |
| 444 mnemonic = 'cmp' | |
| 445 opcode = 5 # 00101 | |
| 446 operands = (RegOp, Imm8) | |
| 447 def __init__(self, rn, imm): | |
| 448 self.rn = rn | |
| 449 self.imm = imm | |
| 450 def encode(self): | |
| 451 rn = self.rn.num | |
| 452 imm = self.imm.imm | |
| 453 opcode = self.opcode | |
| 454 h = (opcode << 11) | (rn << 8) | imm | |
| 455 return u16(h) | |
| 202 | 456 |
| 219 | 457 # Jumping: |
| 218 | 458 |
| 238 | 459 def wrap_negative(x, bits): |
| 460 b = struct.unpack('<I', struct.pack('<i', x))[0] | |
| 461 mask = (1 << bits) - 1 | |
| 462 return b & mask | |
| 463 | |
| 237 | 464 class jumpBase_ins(ArmInstruction): |
| 465 operands = (LabelRef,) | |
| 205 | 466 def __init__(self, target_label): |
| 237 | 467 assert type(target_label) is LabelRef |
| 205 | 468 self.target = target_label |
| 237 | 469 self.offset = 0 |
| 470 | |
| 471 def resolve(self, f): | |
| 472 la = f(self.target.name) | |
| 238 | 473 sa = self.address + 4 |
| 237 | 474 self.offset = (la - sa) |
| 238 | 475 #if self.offset < 0: |
| 476 # # TODO: handle negative jump | |
| 477 # self.offset = 0 | |
| 237 | 478 |
| 219 | 479 def __repr__(self): |
| 237 | 480 return '{} {}'.format(self.mnemonic, self.target.name) |
| 219 | 481 |
| 482 @armtarget.instruction | |
| 237 | 483 class b_ins(jumpBase_ins): |
| 484 mnemonic = 'B' | |
| 485 def encode(self): | |
| 238 | 486 imm11 = wrap_negative(self.offset >> 1, 11) |
| 487 h = (0b11100 << 11) | imm11 # | 1 # 1 to enable thumb mode | |
| 237 | 488 return u16(h) |
| 489 | |
|
251
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490 @armtarget.instruction |
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491 class bl_ins(jumpBase_ins): |
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492 mnemonic = 'BL' |
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493 def encode(self): |
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494 imm32 = wrap_negative(self.offset >> 1, 32) |
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495 imm11 = imm32 & 0x7FF |
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496 imm10 = (imm32 >> 11) & 0x3FF |
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497 j1 = 1 # TODO: what do these mean? |
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498 j2 = 1 |
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499 s = (imm32 >> 24) & 0x1 |
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500 h1 = (0b11110 << 11) | (s << 10) | imm10 |
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501 h2 = (0b1101 << 12) | (j1 << 13) | (j2 << 11) | imm11 |
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502 return u16(h1) + u16(h2) |
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503 |
| 237 | 504 class cond_base_ins(jumpBase_ins): |
| 505 def encode(self): | |
| 238 | 506 imm8 = wrap_negative(self.offset >> 1, 8) |
| 237 | 507 h = (0b1101 << 12) | (self.cond << 8) | imm8 |
| 508 return u16(h) | |
| 509 | |
| 510 @armtarget.instruction | |
| 511 class beq_ins(cond_base_ins): | |
| 219 | 512 mnemonic = 'beq' |
| 237 | 513 cond = 0 |
| 514 | |
| 515 @armtarget.instruction | |
| 516 class beq_ins(cond_base_ins): | |
| 517 mnemonic = 'bne' | |
| 518 cond = 1 | |
| 205 | 519 |
| 520 @armtarget.instruction | |
| 521 class push_ins(ArmInstruction): | |
| 206 | 522 operands = (RegisterSet,) |
| 205 | 523 mnemonic = 'push' |
| 524 def __init__(self, regs): | |
| 206 | 525 assert (type(regs),) == self.operands, (type(regs),) |
| 205 | 526 self.regs = regs |
| 206 | 527 def __repr__(self): |
| 528 return '{0} {{{1}}}'.format(self.mnemonic, self.regs) | |
| 205 | 529 def encode(self): |
| 206 | 530 reg_list = 0 |
| 531 M = 0 | |
| 532 for n in self.regs.registerNumbers(): | |
| 533 if n < 8: | |
| 534 reg_list |= (1 << n) | |
| 535 elif n == 14: | |
| 536 M = 1 | |
| 537 else: | |
| 538 raise NotImplementedError('not implemented for this register') | |
| 539 h = (0x5a << 9) | (M << 8) | reg_list | |
| 540 return u16(h) | |
| 205 | 541 |
| 542 @armtarget.instruction | |
| 543 class pop_ins(ArmInstruction): | |
| 206 | 544 operands = (RegisterSet,) |
| 205 | 545 mnemonic = 'pop' |
| 546 def __init__(self, regs): | |
| 547 self.regs = regs | |
| 207 | 548 def __repr__(self): |
| 549 return '{0} {{{1}}}'.format(self.mnemonic, self.regs) | |
| 205 | 550 def encode(self): |
| 206 | 551 reg_list = 0 |
| 552 P = 0 | |
| 553 for n in self.regs.registerNumbers(): | |
| 554 if n < 8: | |
| 555 reg_list |= (1 << n) | |
| 556 elif n == 15: | |
| 557 P = 1 | |
| 558 else: | |
| 559 raise NotImplementedError('not implemented for this register') | |
| 560 h = (0x5E << 9) | (P << 8) | reg_list | |
| 561 return u16(h) | |
| 205 | 562 |
| 563 @armtarget.instruction | |
| 202 | 564 class yield_ins(ArmInstruction): |
| 565 operands = () | |
| 566 mnemonic = 'yield' | |
| 567 def encode(self): | |
| 568 return u16(0xbf10) | |
| 569 | |
| 206 | 570 armtarget.check() |
| 571 |