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255
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1 import logging
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211
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2 import ir
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249
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3 from target import Label, Comment, Alignment, LabelRef, Imm32, DebugInfo
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218
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4 import cortexm3 as arm
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211
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5 from ppci import CompilerError
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269
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6 import flowgraph
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7 import registerallocator
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8 from instructionselector import InstructionSelector
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272
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9 import irmach
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275
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10 from irmach import makeIns
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11 import canon
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12 import asm
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274
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13
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14 class ArmFrame(irmach.Frame):
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15 """
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16 Arm specific frame for functions.
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17 """
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275
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18 def __init__(self, name):
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19 # We use r7 as frame pointer.
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20 super().__init__(name)
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21 self.regs = ['r0', 'r1', 'r2', 'r3', 'r4', 'r5', 'r6']
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22 self.rv = ir.Temp('special_RV')
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23 self.p1 = ir.Temp('special_P1')
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24 self.p2 = ir.Temp('special_P2')
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25 self.p3 = ir.Temp('special_P3')
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26 self.p4 = ir.Temp('special_P4')
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27 self.fp = ir.Temp('special_FP')
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28 # Pre-colored registers:
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29 self.tempMap = {}
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30 self.tempMap[self.rv] = 'r0'
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31 self.tempMap[self.p1] = 'r1'
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32 self.tempMap[self.p2] = 'r2'
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33 self.tempMap[self.p3] = 'r3'
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34 self.tempMap[self.p4] = 'r4'
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35 self.tempMap[self.fp] = 'r7'
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36 self.locVars = {}
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37 self.parMap = {}
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38
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39 def argLoc(self, pos):
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40 """
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41 Gets the function parameter location in IR-code format.
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42 """
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43 if pos == 0:
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44 return self.p1
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45 elif pos == 1:
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46 return self.p2
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47 elif pos == 2:
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48 return self.p3
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49 elif pos == 3:
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50 return self.p4
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51 else:
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52 raise NotImplementedError('No more than 4 parameters implemented')
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53
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54 def allocVar(self, lvar):
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55 if lvar not in self.locVars:
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56 self.locVars[lvar] = self.stacksize
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57 self.stacksize = self.stacksize + 4
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58 return self.locVars[lvar]
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59
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60 def EntryExitGlue3(self):
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61 """
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62 Add code for the prologue and the epilogue. Add a label, the
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63 return instruction and the stack pointer adjustment for the frame.
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64 """
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65 self.instructions.insert(0, makeIns('{}:'.format(self.name)))
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66 self.instructions.insert(1, makeIns('push {lr, r7}'))
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67 self.instructions.insert(2, makeIns('mov r7, sp'))
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68 self.instructions.insert(3, makeIns('add sp, sp, {}'.format(self.stacksize)))
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69 self.instructions.append(makeIns('sub sp, sp, {}'.format(self.stacksize)))
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70 self.instructions.append(makeIns('pop {pc,r7}'))
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274
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71
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72
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268
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73 class ArmInstructionSelector(InstructionSelector):
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269
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74 """ Instruction selector for the arm architecture """
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268
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75 def munchExpr(self, e):
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76 if isinstance(e, ir.Alloc):
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77 return 0
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275
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78 elif isinstance(e, ir.Binop) and e.operation == '+' and isinstance(e.b, ir.Const) and e.b.value < 8:
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79 a = self.munchExpr(e.a)
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80 d = self.newTmp()
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81 self.emit('add %d0, %s0, {}'.format(e.b.value), dst=[d], src=[a])
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82 return d
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268
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83 elif isinstance(e, ir.Binop) and e.operation == '+':
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84 a = self.munchExpr(e.a)
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85 b = self.munchExpr(e.b)
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268
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86 d = self.newTmp()
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87 self.emit('add %d0, %s0, %s1', dst=[d], src=[a, b])
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88 return d
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275
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89 elif isinstance(e, ir.Binop) and e.operation == '-' and isinstance(e.b, ir.Const) and e.b.value < 8:
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90 a = self.munchExpr(e.a)
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91 d = self.newTmp()
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92 self.emit('sub %d0, %s0, {}'.format(e.b.value), dst=[d], src=[a])
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93 return d
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269
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94 elif isinstance(e, ir.Binop) and e.operation == '-':
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95 a = self.munchExpr(e.a)
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96 b = self.munchExpr(e.b)
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269
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97 d = self.newTmp()
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98 self.emit('sub %d0, %s0, %s1', dst=[d], src=[a, b])
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99 return d
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268
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100 elif isinstance(e, ir.Binop) and e.operation == '|':
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101 a = self.munchExpr(e.a)
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102 b = self.munchExpr(e.b)
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103 d = self.newTmp()
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104 self.emit('or %d0, %s0, %s1', dst=[d], src=[a, b])
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268
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105 return d
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106 elif isinstance(e, ir.Binop) and e.operation == '<<':
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107 a = self.munchExpr(e.a)
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108 b = self.munchExpr(e.b)
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109 d = self.newTmp()
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110 self.emit('lsl %d0, %s0, %s1', dst=[d], src=[a, b])
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111 return d
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112 elif isinstance(e, ir.Binop) and e.operation == '*':
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113 a = self.munchExpr(e.a)
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114 b = self.munchExpr(e.b)
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115 d = self.newTmp()
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116 self.emit('mul %d0, %s0, %s1', dst=[d], src=[a, b])
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117 return d
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118 elif isinstance(e, ir.Const) and e.value < 256:
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119 d = self.newTmp()
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120 self.emit('mov %d0, {}'.format(e.value), dst=[d])
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121 return d
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122 elif isinstance(e, ir.Mem) and isinstance(e.e, ir.Binop) and \
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123 e.e.operation == '+' and isinstance(e.e.b, ir.Const):
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124 base = self.munchExpr(e.e.a)
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125 d = self.newTmp()
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126 self.emit('ldr %d0, [%s0 + {}]'.format(e.e.b.value), src=[base], dst=[d])
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127 return d
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128 elif isinstance(e, ir.Mem):
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129 # Load from memory
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130 base = self.munchExpr(e.e)
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131 d = self.newTmp()
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132 self.emit('ldr %d0, [%s0]', src=[base], dst=[d])
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133 return d
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134 elif isinstance(e, ir.Temp):
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135 return e
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272
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136 elif isinstance(e, ir.Call):
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275
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137 # Move arguments into proper locations:
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138 reguses = []
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139 for i, a in enumerate(e.arguments):
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140 loc = self.frame.argLoc(i)
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141 m = ir.Move(loc, a)
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142 self.munchStm(m)
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143 if isinstance(loc, ir.Temp):
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144 reguses.append(loc)
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145 self.emit('bl {}'.format(e.f.name), src=reguses, dst=[self.frame.rv])
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146 d = self.newTmp()
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147 self.move(d, self.frame.rv)
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148 return d
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268
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149 else:
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272
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150 raise NotImplementedError('Expr --> {}'.format(e))
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268
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151
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152 def munchStm(self, s):
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275
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153 if isinstance(s, ir.Terminator):
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154 pass
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155 elif isinstance(s, ir.Move) and isinstance(s.dst, ir.Mem) and isinstance(s.dst.e, ir.Binop) and s.dst.e.operation == '+' and isinstance(s.dst.e.a, ir.Temp) and isinstance(s.dst.e.b, ir.Const):
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156 val = self.munchExpr(s.src)
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157 self.emit('str %s1, [%s0 + {}]'.format(s.dst.e.b.value), src=[s.dst.e.a, val])
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158 elif isinstance(s, ir.Move) and isinstance(s.dst, ir.Mem):
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159 memloc = self.munchExpr(s.dst.e)
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160 val = self.munchExpr(s.src)
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161 self.emit('str %s1, [%s0]', src=[memloc, val])
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162 elif isinstance(s, ir.Move) and isinstance(s.dst, ir.Temp):
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163 val = self.munchExpr(s.src)
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164 dreg = s.dst
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165 self.emit('mov %d0, %s0', dst=[dreg], src=[val])
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275
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166 elif isinstance(s, ir.Exp):
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167 # Generate expression code and discard the result.
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168 x = self.munchExpr(s.e)
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169 self.emit('mov r0, r0', src=[x])
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268
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170 elif isinstance(s, ir.Jump):
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171 tgt = self.targets[s.target]
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172 self.emit('b {}'.format(s.target.name), jumps=[tgt])
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268
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173 elif isinstance(s, ir.CJump):
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174 a = self.munchExpr(s.a)
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175 b = self.munchExpr(s.b)
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176 self.emit('cmp %s0, %s1', src=[a, b])
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177 ntgt = self.targets[s.lab_no]
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178 ytgt = self.targets[s.lab_yes]
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179 jmp_ins = makeIns('jmp {}'.format(s.lab_no.name), jumps=[ntgt])
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269
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180 # Explicitely add fallthrough:
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181 self.emit('jeq %l0', jumps=[ytgt, jmp_ins])
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269
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182 self.emit2(jmp_ins)
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183 else:
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184 raise NotImplementedError('Stmt --> {}'.format(s))
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268
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185
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186
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274
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187 # TODO: this class could be target independent:
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188 class ArmCodeGenerator:
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268
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189 def __init__(self, outs):
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269
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190 # TODO: schedule traces in better order.
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191 # This is optional!
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268
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192 self.ins_sel = ArmInstructionSelector()
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193 self.outs = outs
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194 self.outs.getSection('code').address = 0x08000000
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195 self.outs.getSection('data').address = 0x20000000
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196
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270
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197 def useUnused(self, inslist):
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198 # Use unused temporaries at the end of the list
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199 defTemps = []
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272
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200 useTemps = []
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201 for i in inslist:
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202 for d in iter(i.dst):
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203 defTemps.append(d)
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204 for s in iter(i.src):
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205 useTemps.append(s)
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206 defTemps = set(defTemps)
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207 useTemps = set(useTemps)
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208 unUsed = defTemps - useTemps
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209 assert not unUsed
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210 for uu in unUsed:
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211 inslist.append(irmach.AbstractInstruction('use %s0', src=[uu]))
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212 #print(useTemps)
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270
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213
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214 def allocFrame(self, f):
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215 """
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216 Do register allocation for a single stack frame.
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217 """
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218 ilist = f.instructions
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219 self.useUnused(ilist)
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220 cfg = flowgraph.FlowGraph(ilist)
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221 f.cfg = cfg
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222 ig = registerallocator.InterferenceGraph(cfg)
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223 f.ig = ig
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269
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224
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225 ra = registerallocator.RegisterAllocator()
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226 regMap = ra.registerAllocate(ig, f.regs, f.tempMap)
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272
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227 # Use allocated registers:
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228 for i in ilist:
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229 i.src = tuple(regMap[t] for t in i.src)
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230 i.dst = tuple(regMap[t] for t in i.dst)
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275
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231
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232 def generateFunc(self, irfunc):
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233 # Create a frame for this function:
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234 frame = ArmFrame(irfunc.name)
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235 # Canonicalize the intermediate language:
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236 canon.make(irfunc, frame)
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237 # print('after canonicalize:')
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238 # irfunc.dump()
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239 self.ins_sel.munchFunction(irfunc, frame)
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240 # print('Selected instructions:')
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241 #for i in frame.instructions:
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242 # print(i)
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243
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244 # Do register allocation:
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245 self.allocFrame(frame)
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246 # TODO: Peep-hole here?
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247
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248 # Add label and return and stack adjustment:
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249 frame.EntryExitGlue3()
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250 return frame
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274
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251
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252 def generate(self, ircode):
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253 # Munch program into a bunch of frames. One frame per function.
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254 # Each frame has a flat list of abstract instructions.
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275
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255 # Generate code for all functions:
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256 self.frames = [self.generateFunc(func) for func in ircode.Functions]
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274
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257
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275
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258 # Materialize assembly
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259 # Reparse the register allocated instructions into a stream of
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260 # real instructions.
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261 # TODO: this is ugly via string representations. This could be
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262 # another interface?
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263 assembler = asm.Assembler(target=arm.armtarget, stream=self.outs)
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264 self.outs.selectSection('code')
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265 for frame in self.frames:
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266 for i in frame.instructions:
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267 assembler.assemble_line(str(i))
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268
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268
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275
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269 return self.frames
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268
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270
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