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255
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1 import logging
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211
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2 import ir
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249
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3 from target import Label, Comment, Alignment, LabelRef, Imm32, DebugInfo
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218
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4 import cortexm3 as arm
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211
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5 from ppci import CompilerError
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269
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6 import flowgraph
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7 import registerallocator
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8 from instructionselector import InstructionSelector
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272
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9 import irmach
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262
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10
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274
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11
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12 class ArmFrame(irmach.Frame):
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13 """
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14 Arm specific frame for functions.
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15 """
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16 pass
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17
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18
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268
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19 class ArmInstructionSelector(InstructionSelector):
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269
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20 """ Instruction selector for the arm architecture """
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274
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21 def newFrame(self, name):
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22 return ArmFrame(name)
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23
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268
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24 def munchExpr(self, e):
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25 if isinstance(e, ir.Alloc):
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26 return 0
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27 elif isinstance(e, ir.Binop) and e.operation == '+':
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28 a = self.munchExpr(e.value1)
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29 b = self.munchExpr(e.value2)
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30 d = self.newTmp()
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31 self.emit('add %d0, %s0, %s1', dst=[d], src=[a, b])
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32 return d
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269
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33 elif isinstance(e, ir.Binop) and e.operation == '-':
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34 a = self.munchExpr(e.value1)
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35 b = self.munchExpr(e.value2)
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36 d = self.newTmp()
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37 self.emit('sub %d0, %s0, %s1', dst=[d], src=[a, b])
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38 return d
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268
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39 elif isinstance(e, ir.Binop) and e.operation == '|':
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40 a = self.munchExpr(e.value1)
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41 b = self.munchExpr(e.value2)
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42 d = self.newTmp()
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269
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43 self.emit('or %d0, %s0, %s1', dst=[d], src=[a, b])
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268
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44 return d
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45 elif isinstance(e, ir.Binop) and e.operation == '<<':
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46 a = self.munchExpr(e.value1)
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47 b = self.munchExpr(e.value2)
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48 d = self.newTmp()
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49 self.emit('lsl %d0, %s0, %s1', dst=[d], src=[a, b])
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50 return d
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51 elif isinstance(e, ir.Binop) and e.operation == '*':
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52 a = self.munchExpr(e.value1)
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53 b = self.munchExpr(e.value2)
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54 d = self.newTmp()
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55 self.emit('mul %d0, %s0, %s1', dst=[d], src=[a, b])
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268
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56 return d
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57 elif isinstance(e, ir.Const):
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58 d = self.newTmp()
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59 if e.value < 256:
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60 self.emit('ldr %d0, {}'.format(e.value), dst=[d])
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61 else:
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269
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62 self.emit('ldrpcrel TODO', dst=[d])
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63 return d
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64 elif isinstance(e, ir.Mem):
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65 # Load from memory
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66 loc = self.munchExpr(e.e)
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67 d = self.newTmp()
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68 self.emit('ldr %d0, [%s0]', src=[loc], dst=[d])
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69 return d
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70 elif isinstance(e, ir.Temp):
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269
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71 return self.getTempReg(e)
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274
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72 elif isinstance(e, ir.Parameter):
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73 offset = 1337 # TODO: determine offset in frame??
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74 d = self.newTmp()
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75 self.emit('ldr %d0, [sp + {}]'.format(offset), dst=[d])
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76 return d
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272
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77 elif isinstance(e, ir.Call):
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78 args = [self.munchExpr(a) for a in e.arguments]
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274
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79 frame_size = 222 # TODO: determine frame size?
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80 self.emit('add sp, sp, {}'.format(frame_size))
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272
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81 # TODO: save frame
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82 for a in args:
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83 self.emit('push %s0', src=[a])
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84 self.emit('bl {}'.format(e.f.name))
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85 self.emit('sub sp, sp, 22')
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268
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86 else:
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272
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87 raise NotImplementedError('Expr --> {}'.format(e))
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268
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88
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89 def munchStm(self, s):
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90 if isinstance(s, ir.Move) and isinstance(s.dst, ir.Mem):
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91 memloc = self.munchExpr(s.dst.e)
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92 val = self.munchExpr(s.src)
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93 self.emit('str [%s0], %s1', src=[memloc, val])
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268
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94 elif isinstance(s, ir.Move) and isinstance(s.dst, ir.Temp):
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95 val = self.munchExpr(s.src)
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96 dreg = self.getTempReg(s.dst)
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97 self.emit('mov %d0, %s0', dst=[dreg], src=[val])
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98 elif isinstance(s, ir.Jump):
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99 tgt = self.targets[s.target]
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100 self.emit('jmp %l0', jumps=[tgt])
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101 elif isinstance(s, ir.CJump):
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102 a = self.munchExpr(s.a)
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103 b = self.munchExpr(s.b)
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104 self.emit('cmp %s0, %s1', src=[a, b])
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105 ntgt = self.targets[s.lab_no]
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106 ytgt = self.targets[s.lab_yes]
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107 jmp_ins = self.makeIns('jmp %l0', jumps=[ntgt])
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269
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108 # Explicitely add fallthrough:
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109 self.emit('jeq %l0', jumps=[ytgt, jmp_ins])
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110 self.emit2(jmp_ins)
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274
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111 elif isinstance(s, ir.Terminator):
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112 pass
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113 else:
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114 raise NotImplementedError('Stmt --> {}'.format(s))
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268
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115
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116
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274
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117 # TODO: this class could be target independent:
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118 class ArmCodeGenerator:
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268
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119 def __init__(self, outs):
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120 # TODO: schedule traces in better order.
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121 # This is optional!
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122 self.ins_sel = ArmInstructionSelector()
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123 self.outs = outs
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124 self.outs.getSection('code').address = 0x08000000
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125 self.outs.getSection('data').address = 0x20000000
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126
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270
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127 def useUnused(self, inslist):
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128 # Use unused temporaries at the end of the list
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129 defTemps = []
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272
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130 useTemps = []
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131 for i in inslist:
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132 for d in iter(i.dst):
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133 defTemps.append(d)
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134 for s in iter(i.src):
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135 useTemps.append(s)
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136 defTemps = set(defTemps)
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137 useTemps = set(useTemps)
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138 unUsed = defTemps - useTemps
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139 print('Unused:', unUsed)
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140 for uu in unUsed:
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141 inslist.append(irmach.AbstractInstruction('use %s0', src=[uu]))
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142 #print(useTemps)
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270
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143
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274
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144 def allocFrame(self, f):
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145 """
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146 Do register allocation for a single stack frame.
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147 """
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148 ilist = f.instructions
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149 self.useUnused(ilist)
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150 cfg = flowgraph.FlowGraph(ilist)
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151 f.cfg = cfg
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152 ig = registerallocator.InterferenceGraph(cfg)
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153 f.ig = ig
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269
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154
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155 regs = ['r0', 'r1', 'r2', 'r3', 'r4', 'r5', 'r6', 'r7']
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156 ra = registerallocator.RegisterAllocator()
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270
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157 regMap = ra.registerAllocate(ig, regs)
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272
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158 #print(regMap)
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159 # Use allocated registers:
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160 for i in ilist:
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161 i.src = tuple(regMap[t] for t in i.src)
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162 i.dst = tuple(regMap[t] for t in i.dst)
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272
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163 #print(i)
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274
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164
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165 def generate(self, ircode):
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166 # Munch program into a bunch of frames. One frame per function.
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167 # Each frame has a flat list of abstract instructions.
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168 frames = self.ins_sel.munchProgram(ircode)
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169 self.frames = frames
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170 for f in frames:
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171 self.allocFrame(f)
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172
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173 # TODO: Peep-hole here
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174 # TODO: Materialize assembly
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175 return frames
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268
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176
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177
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