261
|
1 import struct
|
290
|
2 from .basetarget import Register, Instruction, Target, Label, LabelRef
|
|
3 from .basetarget import Imm32, Imm8, Imm7, Imm3
|
292
|
4 from .arminstructions import allins, Reg8Op, ArmRegister
|
|
5 from .arminstructions import Dcd, B
|
|
6 from .arminstructions import R0, R1, R2, R3, R4, R5, R6, R7, LR, PC, SP
|
202
|
7
|
322
|
8 from .armframe import ArmFrame
|
|
9 from .arminstructionselector import ArmInstructionSelector
|
290
|
10
|
|
11 """ ARM target description. """
|
287
|
12
|
218
|
13 # TODO: encode this in DSL (domain specific language)
|
275
|
14 # TBD: is this required?
|
292
|
15 # TODO: make a difference between armv7 and armv5?
|
219
|
16
|
277
|
17
|
292
|
18 class ArmTarget(Target):
|
|
19 def __init__(self):
|
|
20 super().__init__('arm')
|
|
21 for i in allins:
|
|
22 self.addInstruction(i)
|
|
23 # TODO: fix this nicer?
|
|
24 #setattr(self, i.__name__, i)
|
|
25 self.check()
|
322
|
26 self.ins_sel = ArmInstructionSelector()
|
|
27 self.FrameClass = ArmFrame
|