|
404
|
1
|
|
|
2 ; This file contains the low level assembly code required for interrupt
|
|
|
3 ; handling and virtual memory.
|
|
340
|
4
|
|
385
|
5 section reset
|
|
375
|
6
|
|
|
7 interrupt_vector_table:
|
|
389
|
8 ivt_reset: B start ; 0x0 reset
|
|
|
9 ivt_undef: B undef_handler ; 0x4 undefined instruction
|
|
|
10 ivt_svc: B undef_handler ; 0x08 Supervisor call
|
|
375
|
11 ivt_prefetch: B undef_handler ; 0x0C prefetch abort
|
|
389
|
12 ivt_data: B undef_handler ; 0x10 data abort
|
|
|
13 ivt_hyptrap: B undef_handler ; 0x14 not used
|
|
|
14 ivt_irq: B undef_handler ; 0x18 IRQ
|
|
|
15 ivt_fiq: B undef_handler ; 0x18 FIQ
|
|
375
|
16
|
|
|
17
|
|
|
18 start:
|
|
|
19
|
|
404
|
20 ; Setup the memory manager and the stack before entering kernel
|
|
|
21
|
|
375
|
22 ; Setup TTBR1 (translation table base register)
|
|
|
23
|
|
381
|
24 ldr r0, =kernel_table0 ; pseudo instruction which loads the value of the symbol
|
|
|
25 ; -KERNEL_BASE
|
|
375
|
26 mcr p15, 0, r0, c2, c0, 1 ; TTBR1
|
|
|
27 mcr p15, 0, r0, c2, c0, 0 ; TTBR0
|
|
|
28
|
|
|
29 ; Prepare the TTBCR (translation table base control register)
|
|
|
30 mov r0, 0x1 ; TBD: why set this to 1?
|
|
|
31 mcr p15, 0, r0, c2, c0, 2
|
|
|
32
|
|
386
|
33
|
|
|
34 ; Set domain 0 to manager:
|
|
|
35 mov r0, 3
|
|
|
36 mcr p15, 0, r0, c3, c0, 0
|
|
|
37
|
|
|
38
|
|
375
|
39 ; Enable the VMSA (Virtual memory system architecture):
|
|
|
40 mrc p15, 0, r0, c1, c0, 0
|
|
|
41 ; TODO:
|
|
388
|
42 mov r1, 0x1
|
|
|
43 orr r0, r0, r1 ; TODO: implement orr r0, r0, 1
|
|
375
|
44 mcr p15, 0, r0, c1, c0, 0
|
|
|
45
|
|
|
46 ; Setup stack:
|
|
352
|
47 mov sp, 0x30000
|
|
404
|
48 BL kernel_start ; Branch to main (this is actually in the interrupt vector)
|
|
352
|
49 local_loop:
|
|
|
50 B local_loop
|
|
362
|
51
|
|
|
52
|
|
375
|
53 ; Interrupt handlers:
|
|
|
54
|
|
|
55 undef_handler:
|
|
|
56 B undef_handler
|
|
|
57
|
|
381
|
58
|
|
|
59 ; Assembly language helpers:
|
|
362
|
60 ; Called to identify the proc:
|
|
381
|
61 arch_pfr0:
|
|
362
|
62 mrc p15, 0, r0, c0, c1, 0
|
|
|
63 mov pc, lr
|
|
|
64
|
|
381
|
65 arch_pfr1:
|
|
362
|
66 mrc p15, 0, r0, c0, c1, 1
|
|
|
67 mov pc, lr
|
|
|
68
|
|
381
|
69 arch_mmfr0:
|
|
362
|
70 mrc p15, 0, r0, c0, c1, 4
|
|
|
71 mov pc, lr
|
|
|
72
|
|
381
|
73 arch_mpuir:
|
|
362
|
74 mrc p15, 0, r0, c0, c0, 4
|
|
|
75 mov pc, lr
|
|
381
|
76
|
|
|
77
|
|
|
78 ; Memory map tables:
|
|
|
79
|
|
|
80 section mem_tables
|
|
|
81
|
|
|
82 kernel_table0:
|
|
388
|
83 dcd 0x00000402 ; Identity map first 1 MB
|
|
|
84 dcd 0x10000402 ; Map to peripheral space 1 MB
|
|
|
85 repeat 0x5FE
|
|
386
|
86 dcd 0
|
|
|
87 endrepeat
|
|
381
|
88
|
|
388
|
89 dcd 0x00000402 ; Alias to 0x0
|
|
|
90
|
|
|
91 repeat 0x9FF
|
|
|
92 dcd 0
|
|
|
93 endrepeat
|
|
|
94
|
