|
340
|
1
|
|
375
|
2
|
|
|
3 interrupt_vector_table:
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|
|
4 ivt_reset: B start ; 0x0 reset
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|
|
5 ivt_undef: B undef_handler ; 0x4 undefined instruction
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|
|
6 ivt_svc: B undef_handler ; 0x08 Supervisor call
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|
|
7 ivt_prefetch: B undef_handler ; 0x0C prefetch abort
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|
|
8 ivt_data: B undef_handler ; 0x10 data abort
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|
|
9 ivt_hyptrap: B undef_handler ; 0x14 not used
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|
|
10 ivt_irq: B undef_handler ; 0x18 IRQ
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|
|
11 ivt_fiq: B undef_handler ; 0x18 FIQ
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|
|
12
|
|
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13
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|
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14 start:
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15
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|
|
16 ; Setup TTBR1 (translation table base register)
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17
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18 mov r0, 0
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19 mcr p15, 0, r0, c2, c0, 1 ; TTBR1
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20 mcr p15, 0, r0, c2, c0, 0 ; TTBR0
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|
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21
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|
|
22 ; Prepare the TTBCR (translation table base control register)
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23 mov r0, 0x1 ; TBD: why set this to 1?
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24 mcr p15, 0, r0, c2, c0, 2
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25
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26 ; Enable the VMSA (Virtual memory system architecture):
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27 mrc p15, 0, r0, c1, c0, 0
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|
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28 ; TODO:
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29 ; orr r0, r0, 0x1
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|
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30 mcr p15, 0, r0, c1, c0, 0
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|
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31
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|
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32 ; Setup stack:
|
|
352
|
33 mov sp, 0x30000
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34 BL kernel_start ; Branch to main (this is actually in the interrupt vector)
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|
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35 local_loop:
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36 B local_loop
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|
362
|
37
|
|
|
38
|
|
375
|
39 ; Interrupt handlers:
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|
|
40
|
|
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41 undef_handler:
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|
|
42 B undef_handler
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|
|
43
|
|
362
|
44 ; Called to identify the proc:
|
|
367
|
45 archmem_pfr0:
|
|
362
|
46 mrc p15, 0, r0, c0, c1, 0
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|
|
47 mov pc, lr
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|
|
48
|
|
367
|
49 archmem_pfr1:
|
|
362
|
50 mrc p15, 0, r0, c0, c1, 1
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|
|
51 mov pc, lr
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|
|
52
|
|
367
|
53 archmem_mmfr0:
|
|
362
|
54 mrc p15, 0, r0, c0, c1, 4
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|
|
55 mov pc, lr
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|
|
56
|
|
|
57
|
|
367
|
58 archmem_mpuir:
|
|
362
|
59 mrc p15, 0, r0, c0, c0, 4
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|
|
60 mov pc, lr
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