; This file contains the low level assembly code required for interrupt
; handling and virtual memory.

section reset

interrupt_vector_table:
ivt_reset: B start            ; 0x0 reset
ivt_undef: B undef_handler    ; 0x4 undefined instruction
ivt_svc: B undef_handler      ; 0x08 Supervisor call
ivt_prefetch: B undef_handler ; 0x0C prefetch abort
ivt_data: B undef_handler     ; 0x10 data abort
ivt_hyptrap: B undef_handler  ; 0x14 not used
ivt_irq: B undef_handler      ; 0x18 IRQ
ivt_fiq: B undef_handler      ; 0x18 FIQ


start:

; Setup the memory manager and the stack before entering kernel

; Setup TTBR1 (translation table base register)

ldr r0, =kernel_table0    ; pseudo instruction which loads the value of the symbol
; -KERNEL_BASE
mcr p15, 0, r0, c2, c0, 1 ; TTBR1
mcr p15, 0, r0, c2, c0, 0 ; TTBR0

; Prepare the TTBCR (translation table base control register)
mov r0, 0x1  ; TBD: why set this to 1?
mcr p15, 0, r0, c2, c0, 2


; Set domain 0 to manager:
mov r0, 3
mcr p15, 0, r0, c3, c0, 0


; Enable the VMSA (Virtual memory system architecture):
mrc p15, 0, r0, c1, c0, 0
; TODO:
mov r1, 0x1
orr r0, r0, r1 ; TODO: implement orr r0, r0, 1
mcr p15, 0, r0, c1, c0, 0

; Setup stack:
mov sp, 0x30000
BL kernel_start  ; Branch to main (this is actually in the interrupt vector)
local_loop:
B local_loop


; Interrupt handlers:

undef_handler:
B undef_handler


; Assembly language helpers:
; Called to identify the proc:
arch_pfr0:
mrc p15, 0, r0, c0, c1, 0
mov pc, lr

arch_pfr1:
mrc p15, 0, r0, c0, c1, 1
mov pc, lr

arch_mmfr0:
mrc p15, 0, r0, c0, c1, 4
mov pc, lr

arch_mpuir:
mrc p15, 0, r0, c0, c0, 4
mov pc, lr


; Memory map tables:

section mem_tables

kernel_table0:
 dcd 0x00000402 ; Identity map first 1 MB
 dcd 0x10000402 ; Map to peripheral space 1 MB
 repeat 0x5FE
 dcd 0
 endrepeat

 dcd 0x00000402 ; Alias to 0x0

 repeat 0x9FF
 dcd 0
 endrepeat