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255
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1 import logging
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211
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2 import ir
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249
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3 from target import Label, Comment, Alignment, LabelRef, Imm32, DebugInfo
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218
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4 import cortexm3 as arm
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211
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5 from ppci import CompilerError
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261
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6 import irmach
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211
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7
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262
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8
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9 class InstructionSelector:
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268
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10 def newTmp(self):
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11 return 't999'
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12
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13 def munchProgram(self, p):
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14 assert isinstance(p, ir.Module)
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15 self.result = []
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16 for f in p.Functions:
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17 for bb in f.BasicBlocks:
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18 for i in bb.Instructions:
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19 self.munchStm(i)
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20 return self.result
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21
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22 def emit(self, *args, **kwargs):
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23 """ Abstract instruction emitter """
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24 i = irmach.AbstractInstruction(*args, **kwargs)
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25 self.result.append(i)
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26
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27 def munchStm(self, s):
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28 raise NotImplementedError()
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29
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30 def munchExpr(self, e):
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31 raise NotImplementedError()
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262
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32
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33
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34 class RegisterAllocator:
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268
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35 """ Target independent register allocator """
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262
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36 pass
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37
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38
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268
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39 class ArmInstructionSelector(InstructionSelector):
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40 def munchExpr(self, e):
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41 if isinstance(e, ir.Alloc):
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42 return 0
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43 elif isinstance(e, ir.Binop) and e.operation == '+':
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44 a = self.munchExpr(e.value1)
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45 b = self.munchExpr(e.value2)
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46 d = self.newTmp()
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47 self.emit('add %d0, %s0, %s1', dst=[d], src=[a, b])
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48 return d
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49 elif isinstance(e, ir.Binop) and e.operation == '|':
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50 a = self.munchExpr(e.value1)
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51 b = self.munchExpr(e.value2)
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52 d = self.newTmp()
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53 self.emit('orrrr %d0, %s0, %s1', dst=[d], src=[a, b])
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54 return d
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55 elif isinstance(e, ir.Binop) and e.operation == '<<':
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56 a = self.munchExpr(e.value1)
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57 b = self.munchExpr(e.value2)
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58 d = self.newTmp()
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59 self.emit('lsl %d0, %s0, %s1', dst=[d], src=[a, b])
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60 return d
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61 elif isinstance(e, ir.Binop) and e.operation == '*':
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62 a = self.munchExpr(e.value1)
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63 b = self.munchExpr(e.value2)
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64 d = self.newTmp()
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65 self.emit('mylll %d0, %s0, %s1', dst=[d], src=[a, b])
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66 return d
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67 elif isinstance(e, ir.Const):
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68 d = self.newTmp()
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69 if e.value < 256:
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70 self.emit('ldr %d0, {}'.format(e.value), dst=[d])
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71 else:
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72 self.emit('ldrpcrel TODO')
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73 return d
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74 elif isinstance(e, ir.Mem):
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75 # Load from memory
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76 loc = self.munchExpr(e.e)
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77 d = self.newTmp()
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78 self.emit('ldr %d0, [%s0]', src=[loc], dst=[d])
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79 return d
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80 elif isinstance(e, ir.Temp):
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81 return e
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82 else:
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83 raise NotImplementedError('--> {}'.format(e))
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84
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85 def munchStm(self, s):
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86 if isinstance(s, ir.Move) and isinstance(s.dst, ir.Mem):
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87 memloc = self.munchExpr(s.dst.e)
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88 val = self.munchExpr(s.src)
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89 self.emit('str [%s0], %s1')
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90 elif isinstance(s, ir.Move) and isinstance(s.dst, ir.Temp):
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91 val = self.munchExpr(s.src)
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92 self.emit('str %d0, %s0', dst=[s.dst], src=[val])
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93 elif isinstance(s, ir.Return):
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94 self.emit('ret')
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95 elif isinstance(s, ir.Jump):
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96 self.emit('jmp {}'.format(s))
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97 elif isinstance(s, ir.CJump):
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98 self.munchExpr(s.a)
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99 self.munchExpr(s.b)
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100 self.emit('jmp {}'.format(s))
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101 else:
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102 raise NotImplementedError('--> {}'.format(s))
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103
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104
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211
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105 class ArmCodeGenerator:
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268
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106 def __init__(self, outs):
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107 self.ins_sel = ArmInstructionSelector()
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108 self.outs = outs
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109 self.outs.getSection('code').address = 0x08000000
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110 self.outs.getSection('data').address = 0x20000000
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111
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112 def generate(self, ircode):
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113 self.ins_sel.munchProgram(ircode)
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114
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115
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116 class ArmCodeGenerator_old:
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219
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117 """
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118 Simple code generator
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119 Ad hoc implementation
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120 """
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211
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121 def __init__(self, out):
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122 self.outs = out
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258
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123 self.logger = logging.getLogger('codegenarm')
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211
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124
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125 def emit(self, item):
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126 self.outs.emit(item)
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127
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128 def generate(self, ircode):
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129 assert isinstance(ircode, ir.Module)
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255
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130 self.logger.info('Generating arm code for {}'.format(ircode.name))
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261
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131 self.available_regs = {arm.r3, arm.r4, arm.r5, arm.r6, arm.r7}
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258
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132 self.regmap = {}
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250
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133 # TODO: get these from linker descriptor?
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134 self.outs.getSection('code').address = 0x08000000
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135 self.outs.getSection('data').address = 0x20000000
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211
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136 self.outs.selectSection('data')
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137
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138 for gvar in ircode.Variables:
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235
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139 self.emit(Label(gvar.name))
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211
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140 # TODO: use initial value:
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235
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141 self.dcd(0)
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211
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142
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143 self.imms = [] # list with immediates relative to PC.
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144 self.outs.selectSection('code')
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232
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145
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146 # Manually inserted startup code:
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235
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147 self.dcd(0x20000678) # initial stack ptr
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237
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148 # TODO: use label here:
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149 #self.emit(arm.dcd_ins(LabelRef('reset'))) # reset vector
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150 self.dcd(0x08000009) # reset vector, lsb indicates thumb mode
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259
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151 self.emit(arm.bl_ins(LabelRef('main')))
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232
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152
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237
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153 self.emit(Label('reset'))
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211
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154 for f in ircode.Functions:
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240
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155 self.localVars = []
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219
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156 # Add global variable addresses to immediate list:
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157 for gvar in ircode.Variables:
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158 pass #self.imms.append((
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159
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160 self.stack_frame = []
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234
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161 self.emit(Label(f.name))
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218
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162 # Save some registers:
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261
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163 self.emit(arm.push_ins(arm.RegisterSet({arm.r3, arm.r4, arm.r5, arm.r6,arm.r7,arm.lr})))
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211
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164 for bb in f.BasicBlocks:
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234
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165 self.emit(Label(bb.name))
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211
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166 for ins in bb.Instructions:
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167 self.generateInstruction(ins)
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168
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235
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169 self.align()
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219
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170 while self.imms:
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171 l, v = self.imms.pop()
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234
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172 self.emit(Label(l))
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235
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173 self.dcd(v)
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174 self.align()
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237
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175 self.outs.backpatch()
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176 self.outs.backpatch()
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258
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177 codesize = self.outs.getSection('code').Size
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178 self.logger.info('Generated {} bytes code'.format(codesize))
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219
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179
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235
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180 def dcd(self, x):
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181 self.emit(arm.dcd_ins(Imm32(x)))
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182
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183 def align(self):
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184 self.outs.emit(Alignment(4))
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249
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185
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225
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186 # Helper functions:
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219
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187 def getStack(self, v):
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188 off = self.stack_frame.index(v)
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189 return off * 4
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249
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190
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219
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191 def addStack(self, v):
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192 self.stack_frame.append(v)
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193 return self.getStack(v)
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249
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194
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219
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195 def getGlobal(self, r, g):
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196 _global_address = g.name + '__global'
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235
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197 self.emit(arm.ldr_pcrel(r, LabelRef(_global_address)))
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249
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198
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225
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199 def loadStack(self, reg, val):
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200 self.emit(arm.ldr_sprel(reg, arm.MemSpRel(self.getStack(val))))
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249
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201
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258
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202 def getreg(self, v):
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203 if not v in self.regmap:
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204 self.regmap[v] = self.available_regs.pop()
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205 return self.regmap[v]
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206
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207 def freereg(self, v, ins):
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208 if v.lastUse(ins):
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209 r = self.regmap.pop(v)
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210 assert r not in self.regmap.values()
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211 self.available_regs.add(r)
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212
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225
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213 def comment(self, txt):
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234
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214 self.emit(Comment(txt))
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219
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215
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249
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216 def debugInfo(self, loc):
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217 if loc:
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218 self.emit(DebugInfo(loc))
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219
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211
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220 def generateInstruction(self, ins):
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232
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221 self.comment(str(ins))
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249
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222 if hasattr(ins, 'debugLoc'):
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223 self.debugInfo(ins.debugLoc)
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211
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224 if type(ins) is ir.Branch:
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237
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225 tgt = LabelRef(ins.target.name)
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226 self.emit(arm.b_ins(tgt))
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219
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227 elif type(ins) is ir.ImmLoad:
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228 lname = ins.target.name + '_ivalue'
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258
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229 r0 = self.getreg(ins.target)
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230 self.emit(arm.ldr_pcrel(r0, LabelRef(lname)))
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219
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231 self.imms.append((lname, ins.value))
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211
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232 elif type(ins) is ir.Store:
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219
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233 # Load value in r0:
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258
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234 r0 = self.getreg(ins.value)
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219
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235 # store in memory:
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232
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236 # TODO: split globals and locals??
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237 #self.getGlobal(arm.r1, ins.location)
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240
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238 # Horrible hack with localVars
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239 if ins.location in self.localVars:
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243
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240 # The value was alloc'ed
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258
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241 self.emit(arm.str_sprel(r0, arm.MemSpRel(self.getStack(ins.location))))
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240
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242 else:
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258
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243 r1 = self.getreg(ins.location)
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244 self.emit(arm.storeimm5_ins(r0, arm.MemR8Rel(r1, 0)))
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259
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245 self.freereg(ins.location, ins)
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258
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246 self.freereg(ins.value, ins)
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211
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247 elif type(ins) is ir.Load:
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232
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248 # TODO: differ global and local??
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249 #self.getGlobal(arm.r0, ins.location)
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258
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250 r0 = self.getreg(ins.value)
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240
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251 if ins.location in self.localVars:
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258
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252 self.emit(arm.ldr_sprel(r0, arm.MemSpRel(self.getStack(ins.location))))
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240
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253 else:
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258
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254 r2 = self.getreg(ins.location)
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255 self.emit(arm.loadimm5_ins(r0, arm.MemR8Rel(r2, 0)))
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259
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256 self.freereg(ins.location, ins)
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211
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257 elif type(ins) is ir.BinaryOperator:
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219
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258 # Load operands:
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258
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259 r0 = self.getreg(ins.value1)
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260 r1 = self.getreg(ins.value2)
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261 r2 = self.getreg(ins.result)
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219
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262 # do operation:
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263 if ins.operation == '+':
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258
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264 self.emit(arm.addregs_ins(r2, r0, r1))
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232
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265 elif ins.operation == '<<':
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258
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266 self.emit(arm.movregreg_ins(r2, r0))
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267 self.emit(arm.lslregs_ins(r2, r1))
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232
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268 elif ins.operation == '|':
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258
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269 self.emit(arm.movregreg_ins(r2, r0))
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270 self.emit(arm.orrregs_ins(r2, r1))
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219
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271 else:
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237
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272 raise NotImplementedError('operation {} not implemented'.format(ins.operation))
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258
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273 self.freereg(ins.value1, ins)
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274 self.freereg(ins.value2, ins)
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259
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275 elif type(ins) is ir.Call:
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276 # TODO: prep parameters:
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277 self.emit(arm.bl_ins(LabelRef(ins.callee.name)))
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219
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278 elif type(ins) is ir.Return:
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261
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279 self.emit(arm.pop_ins(arm.RegisterSet({arm.r3, arm.r4, arm.r5, arm.r6, arm.r7, arm.pc})))
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212
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280 elif type(ins) is ir.ConditionalBranch:
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258
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281 r0 = self.getreg(ins.a)
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282 r1 = self.getreg(ins.b)
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283 self.emit(arm.cmp_ins(r1, r0))
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262
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284 tgt_yes = LabelRef(ins.lab1.name)
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219
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285 if ins.cond == '==':
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286 self.emit(arm.beq_ins(tgt_yes))
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262
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287 elif ins.cond == '<':
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288 self.emit(arm.blt_ins(tgt_yes))
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289 elif ins.cond == '>':
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290 self.emit(arm.bgt_ins(tgt_yes))
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219
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291 else:
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237
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292 raise NotImplementedError('"{}" not covered'.format(ins.cond))
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262
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293 tgt_no = LabelRef(ins.lab2.name)
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294 self.emit(arm.b_ins(tgt_no))
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258
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295 self.freereg(ins.a, ins)
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296 self.freereg(ins.b, ins)
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222
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297 elif type(ins) is ir.Alloc:
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232
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298 # Local variables are added to stack
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222
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299 self.addStack(ins.value)
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240
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300 self.localVars.append(ins.value)
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301 # load address into variable:
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211
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302 else:
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237
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303 raise NotImplementedError('IR "{}" not covered'.format(ins))
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211
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304
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305
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