--- a/python/codegenarm.py	Mon Jul 08 22:21:44 2013 +0200
+++ b/python/codegenarm.py	Tue Jul 09 17:36:31 2013 +0200
@@ -65,10 +65,10 @@
             lname = ins.target.name + '_ivalue'
             self.emit(arm.ldr_pcrel(arm.r0, ALabel(lname)))
             self.imms.append((lname, ins.value))
-            self.emit(arm.str_sprel(arm.r0, self.addStack(ins.target)))
+            self.emit(arm.str_sprel(arm.r0, arm.MemoryOp(arm.sp, self.addStack(ins.target))))
         elif type(ins) is ir.Store:
             # Load value in r0:
-            self.emit(arm.ldr_sprel(arm.r0, self.getStack(ins.value)))
+            self.emit(arm.ldr_sprel(arm.r0, arm.MemoryOp(arm.sp, self.getStack(ins.value))))
             # store in memory:
             self.getGlobal(arm.r1, ins.location)
             self.emit(arm.storeimm5_ins(arm.r0, arm.MemoryOp(arm.r1, 0)))
@@ -76,23 +76,23 @@
             self.getGlobal(arm.r0, ins.location)
             self.emit(arm.loadimm5_ins(arm.r0, arm.MemoryOp(arm.r0, 0)))
             # Store value on stack:
-            self.emit(arm.str_sprel(arm.r0, self.addStack(ins.value)))
+            self.emit(arm.str_sprel(arm.r0, arm.MemoryOp(arm.sp, self.addStack(ins.value))))
         elif type(ins) is ir.BinaryOperator:
             # Load operands:
-            self.emit(arm.ldr_sprel(arm.r0, self.getStack(ins.value1)))
-            self.emit(arm.ldr_sprel(arm.r1, self.getStack(ins.value2)))
+            self.emit(arm.ldr_sprel(arm.r0, arm.MemoryOp(arm.sp, self.getStack(ins.value1))))
+            self.emit(arm.ldr_sprel(arm.r1, arm.MemoryOp(arm.sp, self.getStack(ins.value2))))
             # do operation:
             if ins.operation == '+':
                 self.emit(arm.addregs_ins(arm.r0, arm.r0, arm.r1))
             else:
                 print('operation not implemented', ins.operation)
             # Store value back:
-            self.emit(arm.str_sprel(arm.r0, self.addStack(ins.result)))
+            self.emit(arm.str_sprel(arm.r0, arm.MemoryOp(arm.sp, self.addStack(ins.result))))
         elif type(ins) is ir.Return:
             self.emit(arm.pop_ins(arm.RegisterSet({arm.r4, arm.r5, arm.r6, arm.r7, arm.pc})))
         elif type(ins) is ir.ConditionalBranch:
-            self.emit(arm.ldr_sprel(arm.r0, self.getStack(ins.a)))
-            self.emit(arm.ldr_sprel(arm.r1, self.getStack(ins.b)))
+            self.emit(arm.ldr_sprel(arm.r0, arm.MemoryOp(arm.sp, self.getStack(ins.a))))
+            self.emit(arm.ldr_sprel(arm.r1, arm.MemoryOp(arm.sp, self.getStack(ins.b))))
             self.emit(arm.cmp_ins(arm.r1, arm.r0))
             tgt_yes = ALabel(ins.lab1.name)
             if ins.cond == '==':
@@ -101,6 +101,8 @@
                 print('TODO', ins.cond)
             tgt_no = ALabel(ins.lab2.name)
             self.emit(arm.jmp_ins(tgt_no))
+        elif type(ins) is ir.Alloc:
+            self.addStack(ins.value)
         else:
             raise CompilerError('IR "{}" not covered'.format(ins))