--- a/python/codegenarm.py	Tue Jul 09 17:59:15 2013 +0200
+++ b/python/codegenarm.py	Thu Jul 11 07:42:30 2013 +0200
@@ -1,5 +1,5 @@
 import ir
-from asmnodes import ALabel
+from asmnodes import ALabel, AComment
 import cortexm3 as arm
 from ppci import CompilerError
 
@@ -47,6 +47,7 @@
                 self.emit(arm.dcd_ins(v))
             self.outs.align(4)
 
+    # Helper functions:
     def getStack(self, v):
         off = self.stack_frame.index(v)
         return off * 4
@@ -56,43 +57,53 @@
     def getGlobal(self, r, g):
         _global_address = g.name + '__global'
         self.emit(arm.ldr_pcrel(r, ALabel(_global_address)))
+    def loadStack(self, reg, val):
+        self.emit(arm.ldr_sprel(reg, arm.MemSpRel(self.getStack(val))))
+    def comment(self, txt):
+        self.emit(AComment(txt))
 
     def generateInstruction(self, ins):
         if type(ins) is ir.Branch:
             tgt = ALabel(ins.target.name)
             self.emit(arm.jmp_ins(tgt))
         elif type(ins) is ir.ImmLoad:
+            self.comment(str(ins))
             lname = ins.target.name + '_ivalue'
             self.emit(arm.ldr_pcrel(arm.r0, ALabel(lname)))
             self.imms.append((lname, ins.value))
-            self.emit(arm.str_sprel(arm.r0, arm.MemoryOp(arm.sp, self.addStack(ins.target))))
+            self.emit(arm.str_sprel(arm.r0, arm.MemSpRel(self.addStack(ins.target))))
         elif type(ins) is ir.Store:
+            self.comment(str(ins))
             # Load value in r0:
-            self.emit(arm.ldr_sprel(arm.r0, arm.MemoryOp(arm.sp, self.getStack(ins.value))))
+            self.loadStack(arm.r0, ins.value)
             # store in memory:
             self.getGlobal(arm.r1, ins.location)
-            self.emit(arm.storeimm5_ins(arm.r0, arm.MemoryOp(arm.r1, 0)))
+            self.emit(arm.storeimm5_ins(arm.r0, arm.MemR8Rel(arm.r1, 0)))
         elif type(ins) is ir.Load:
+            self.comment(str(ins))
             self.getGlobal(arm.r0, ins.location)
-            self.emit(arm.loadimm5_ins(arm.r0, arm.MemoryOp(arm.r0, 0)))
+            self.emit(arm.loadimm5_ins(arm.r0, arm.MemR8Rel(arm.r0, 0)))
             # Store value on stack:
-            self.emit(arm.str_sprel(arm.r0, arm.MemoryOp(arm.sp, self.addStack(ins.value))))
+            self.emit(arm.str_sprel(arm.r0, arm.MemSpRel(self.addStack(ins.value))))
         elif type(ins) is ir.BinaryOperator:
+            self.comment(str(ins))
             # Load operands:
-            self.emit(arm.ldr_sprel(arm.r0, arm.MemoryOp(arm.sp, self.getStack(ins.value1))))
-            self.emit(arm.ldr_sprel(arm.r1, arm.MemoryOp(arm.sp, self.getStack(ins.value2))))
+            self.loadStack(arm.r0, ins.value1)
+            self.loadStack(arm.r1, ins.value2)
             # do operation:
             if ins.operation == '+':
                 self.emit(arm.addregs_ins(arm.r0, arm.r0, arm.r1))
             else:
                 print('operation not implemented', ins.operation)
             # Store value back:
-            self.emit(arm.str_sprel(arm.r0, arm.MemoryOp(arm.sp, self.addStack(ins.result))))
+            self.emit(arm.str_sprel(arm.r0, arm.MemSpRel(self.addStack(ins.result))))
         elif type(ins) is ir.Return:
+            self.comment(str(ins))
             self.emit(arm.pop_ins(arm.RegisterSet({arm.r4, arm.r5, arm.r6, arm.r7, arm.pc})))
         elif type(ins) is ir.ConditionalBranch:
-            self.emit(arm.ldr_sprel(arm.r0, arm.MemoryOp(arm.sp, self.getStack(ins.a))))
-            self.emit(arm.ldr_sprel(arm.r1, arm.MemoryOp(arm.sp, self.getStack(ins.b))))
+            self.comment(str(ins))
+            self.loadStack(arm.r0, ins.a)
+            self.loadStack(arm.r1, ins.b)
             self.emit(arm.cmp_ins(arm.r1, arm.r0))
             tgt_yes = ALabel(ins.lab1.name)
             if ins.cond == '==':