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1 import logging
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2 import ir
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3 from target import Label, Comment, Alignment, LabelRef, Imm32, DebugInfo
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4 import cortexm3 as arm
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5 from ppci import CompilerError
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6 import irmach
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7
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8 class ArmCodeGenerator:
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9 """
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10 Simple code generator
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11 Ad hoc implementation
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12 """
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13 def __init__(self, out):
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14 self.outs = out
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15 self.logger = logging.getLogger('codegenarm')
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16
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17 def emit(self, item):
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18 self.outs.emit(item)
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19
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20 def generate(self, ircode):
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21 assert isinstance(ircode, ir.Module)
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22 self.logger.info('Generating arm code for {}'.format(ircode.name))
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23 self.available_regs = {arm.r3, arm.r4, arm.r5, arm.r6, arm.r7}
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24 self.regmap = {}
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25 # TODO: get these from linker descriptor?
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26 self.outs.getSection('code').address = 0x08000000
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27 self.outs.getSection('data').address = 0x20000000
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28 self.outs.selectSection('data')
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29
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30 for gvar in ircode.Variables:
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31 self.emit(Label(gvar.name))
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32 # TODO: use initial value:
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33 self.dcd(0)
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34
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35 self.imms = [] # list with immediates relative to PC.
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36 self.outs.selectSection('code')
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37
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38 # Manually inserted startup code:
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39 self.dcd(0x20000678) # initial stack ptr
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40 # TODO: use label here:
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41 #self.emit(arm.dcd_ins(LabelRef('reset'))) # reset vector
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42 self.dcd(0x08000009) # reset vector, lsb indicates thumb mode
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43 self.emit(arm.bl_ins(LabelRef('main')))
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44
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45 self.emit(Label('reset'))
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46 for f in ircode.Functions:
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47 self.localVars = []
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48 # Add global variable addresses to immediate list:
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49 for gvar in ircode.Variables:
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50 pass #self.imms.append((
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51
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52 self.stack_frame = []
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53 self.emit(Label(f.name))
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54 # Save some registers:
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55 self.emit(arm.push_ins(arm.RegisterSet({arm.r3, arm.r4, arm.r5, arm.r6,arm.r7,arm.lr})))
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56 for bb in f.BasicBlocks:
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57 self.emit(Label(bb.name))
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58 for ins in bb.Instructions:
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59 self.generateInstruction(ins)
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60
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61 self.align()
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62 while self.imms:
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63 l, v = self.imms.pop()
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64 self.emit(Label(l))
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65 self.dcd(v)
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66 self.align()
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67 self.outs.backpatch()
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68 self.outs.backpatch()
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69 codesize = self.outs.getSection('code').Size
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70 self.logger.info('Generated {} bytes code'.format(codesize))
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71
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72 def dcd(self, x):
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73 self.emit(arm.dcd_ins(Imm32(x)))
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74
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75 def align(self):
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76 self.outs.emit(Alignment(4))
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77
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78 # Helper functions:
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79 def getStack(self, v):
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80 off = self.stack_frame.index(v)
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81 return off * 4
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82
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83 def addStack(self, v):
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84 self.stack_frame.append(v)
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85 return self.getStack(v)
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86
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87 def getGlobal(self, r, g):
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88 _global_address = g.name + '__global'
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89 self.emit(arm.ldr_pcrel(r, LabelRef(_global_address)))
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90
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91 def loadStack(self, reg, val):
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92 self.emit(arm.ldr_sprel(reg, arm.MemSpRel(self.getStack(val))))
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93
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94 def getreg(self, v):
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95 if not v in self.regmap:
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96 self.regmap[v] = self.available_regs.pop()
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97 return self.regmap[v]
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98
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99 def freereg(self, v, ins):
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100 if v.lastUse(ins):
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101 r = self.regmap.pop(v)
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102 assert r not in self.regmap.values()
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103 self.available_regs.add(r)
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104
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105 def comment(self, txt):
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106 self.emit(Comment(txt))
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107
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108 def debugInfo(self, loc):
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109 if loc:
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110 self.emit(DebugInfo(loc))
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111
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112 def generateInstruction(self, ins):
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113 self.comment(str(ins))
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114 if hasattr(ins, 'debugLoc'):
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115 self.debugInfo(ins.debugLoc)
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116 if type(ins) is ir.Branch:
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117 tgt = LabelRef(ins.target.name)
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118 self.emit(arm.b_ins(tgt))
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119 elif type(ins) is ir.ImmLoad:
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120 lname = ins.target.name + '_ivalue'
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121 r0 = self.getreg(ins.target)
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122 self.emit(arm.ldr_pcrel(r0, LabelRef(lname)))
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123 self.imms.append((lname, ins.value))
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124 elif type(ins) is ir.Store:
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125 # Load value in r0:
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126 r0 = self.getreg(ins.value)
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127 # store in memory:
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128 # TODO: split globals and locals??
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129 #self.getGlobal(arm.r1, ins.location)
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130 # Horrible hack with localVars
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131 if ins.location in self.localVars:
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132 # The value was alloc'ed
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133 self.emit(arm.str_sprel(r0, arm.MemSpRel(self.getStack(ins.location))))
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134 else:
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135 r1 = self.getreg(ins.location)
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136 self.emit(arm.storeimm5_ins(r0, arm.MemR8Rel(r1, 0)))
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137 self.freereg(ins.location, ins)
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138 self.freereg(ins.value, ins)
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139 elif type(ins) is ir.Load:
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140 # TODO: differ global and local??
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141 #self.getGlobal(arm.r0, ins.location)
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142 r0 = self.getreg(ins.value)
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143 if ins.location in self.localVars:
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144 self.emit(arm.ldr_sprel(r0, arm.MemSpRel(self.getStack(ins.location))))
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145 else:
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146 r2 = self.getreg(ins.location)
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147 self.emit(arm.loadimm5_ins(r0, arm.MemR8Rel(r2, 0)))
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148 self.freereg(ins.location, ins)
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149 elif type(ins) is ir.BinaryOperator:
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150 # Load operands:
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151 r0 = self.getreg(ins.value1)
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152 r1 = self.getreg(ins.value2)
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153 r2 = self.getreg(ins.result)
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154 # do operation:
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155 if ins.operation == '+':
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156 self.emit(arm.addregs_ins(r2, r0, r1))
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157 elif ins.operation == '<<':
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158 self.emit(arm.movregreg_ins(r2, r0))
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159 self.emit(arm.lslregs_ins(r2, r1))
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160 elif ins.operation == '|':
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161 self.emit(arm.movregreg_ins(r2, r0))
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162 self.emit(arm.orrregs_ins(r2, r1))
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163 else:
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164 raise NotImplementedError('operation {} not implemented'.format(ins.operation))
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165 self.freereg(ins.value1, ins)
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166 self.freereg(ins.value2, ins)
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167 elif type(ins) is ir.Call:
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168 # TODO: prep parameters:
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169 self.emit(arm.bl_ins(LabelRef(ins.callee.name)))
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170 elif type(ins) is ir.Return:
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171 self.emit(arm.pop_ins(arm.RegisterSet({arm.r3, arm.r4, arm.r5, arm.r6, arm.r7, arm.pc})))
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172 elif type(ins) is ir.ConditionalBranch:
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173 r0 = self.getreg(ins.a)
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174 r1 = self.getreg(ins.b)
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175 self.emit(arm.cmp_ins(r1, r0))
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176 tgt_yes = Label(ins.lab1.name)
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177 if ins.cond == '==':
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178 self.emit(arm.beq_ins(tgt_yes))
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179 else:
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180 raise NotImplementedError('"{}" not covered'.format(ins.cond))
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181 tgt_no = Label(ins.lab2.name)
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182 self.emit(arm.jmp_ins(tgt_no))
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183 self.freereg(ins.a, ins)
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184 self.freereg(ins.b, ins)
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185 elif type(ins) is ir.Alloc:
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186 # Local variables are added to stack
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187 self.addStack(ins.value)
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188 self.localVars.append(ins.value)
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189 # load address into variable:
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190 else:
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191 raise NotImplementedError('IR "{}" not covered'.format(ins))
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192
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