annotate python/codegenarm.py @ 284:05184b95fa16

Moved tests to seperate folder
author Windel Bouwman
date Fri, 15 Nov 2013 13:43:22 +0100
parents 02385f62f250
children
rev   line source
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1 import logging
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2 import ir
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3 from target import Label, Comment, Alignment, LabelRef, Imm32, DebugInfo, Nop
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4 from target import Imm3
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5 import cortexm3 as arm
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6 from ppci import CompilerError
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7 import registerallocator
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8 from instructionselector import InstructionSelector
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9 import irmach
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10 from irmach import AbstractInstruction as makeIns
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11 import canon
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12 import transform
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13 import asm
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14
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15 class ArmFrame(irmach.Frame):
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16 """
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17 Arm specific frame for functions.
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18 """
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19 def __init__(self, name):
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20 # We use r7 as frame pointer.
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21 super().__init__(name)
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22 self.regs = [arm.r0, arm.r1, arm.r2, arm.r3, arm.r4, arm.r5, arm.r6]
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23 self.rv = ir.Temp('special_RV')
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24 self.p1 = ir.Temp('special_P1')
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25 self.p2 = ir.Temp('special_P2')
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26 self.p3 = ir.Temp('special_P3')
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27 self.p4 = ir.Temp('special_P4')
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28 self.fp = ir.Temp('special_FP')
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29 # Pre-colored registers:
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30 self.tempMap = {}
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31 self.tempMap[self.rv] = arm.r0
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32 self.tempMap[self.p1] = arm.r1
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33 self.tempMap[self.p2] = arm.r2
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34 self.tempMap[self.p3] = arm.r3
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35 self.tempMap[self.p4] = arm.r4
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36 self.tempMap[self.fp] = arm.r7
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37 self.locVars = {}
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38 self.parMap = {}
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39 # Literal pool:
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40 self.constants = []
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41
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42 def argLoc(self, pos):
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43 """
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44 Gets the function parameter location in IR-code format.
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45 """
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46 if pos == 0:
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47 return self.p1
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48 elif pos == 1:
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49 return self.p2
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50 elif pos == 2:
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51 return self.p3
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52 elif pos == 3:
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53 return self.p4
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54 else:
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55 raise NotImplementedError('No more than 4 parameters implemented')
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56
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57 def allocVar(self, lvar):
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58 if lvar not in self.locVars:
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59 self.locVars[lvar] = self.stacksize
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60 self.stacksize = self.stacksize + 4
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61 return self.locVars[lvar]
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62
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63 def addConstant(self, value):
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64 lab_name = '{}_literal_{}'.format(self.name, len(self.constants))
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65 self.constants.append((lab_name, value))
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66 return lab_name
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67
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68 def EntryExitGlue3(self):
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69 """
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70 Add code for the prologue and the epilogue. Add a label, the
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71 return instruction and the stack pointer adjustment for the frame.
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72 """
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73 self.instructions.insert(0, makeIns(arm.Label(self.name)))
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74 self.instructions.insert(1, makeIns(arm.push_ins(arm.RegisterSet({arm.lr, arm.r7}))))
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75 # Reserve stack space for locals:
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76 self.instructions.insert(2, makeIns(arm.subspsp_ins(arm.sp, arm.sp, arm.Imm7(self.stacksize))))
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77 # Setup frame pointer:
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78 self.instructions.insert(3, makeIns(arm.movregreg_ext_ins(arm.r7, arm.sp)))
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79 # Stack grows downwards
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80 self.instructions.append(makeIns(arm.addspsp_ins(arm.sp, arm.sp, arm.Imm7(self.stacksize))))
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81 self.instructions.append(makeIns(arm.pop_ins(arm.RegisterSet({arm.pc, arm.r7}))))
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82 # Add constant literals:
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83 self.instructions.append(makeIns(Alignment(4))) # Align at 4 bytes
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84 for ln, v in self.constants:
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85 self.instructions.append(makeIns(arm.Label(ln)))
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86 self.instructions.append(makeIns(arm.dcd_ins(v)))
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87
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88
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89 class ArmInstructionSelector(InstructionSelector):
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90
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91 """ Instruction selector for the arm architecture """
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92 def munchExpr(self, e):
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93 if isinstance(e, ir.Alloc):
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94 return 0
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95 elif isinstance(e, ir.Binop) and e.operation == '+' and \
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96 isinstance(e.b, ir.Const) and e.b.value < 8:
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97 a = self.munchExpr(e.a)
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98 d = self.newTmp()
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99 c = Imm3(e.b.value)
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100 self.emit(arm.addregregimm3_ins, others=[c], dst=[d], src=[a])
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101 return d
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102 elif isinstance(e, ir.Binop) and e.operation == '+':
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103 a = self.munchExpr(e.a)
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104 b = self.munchExpr(e.b)
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105 d = self.newTmp()
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106 self.emit(arm.addregs_ins, dst=[d], src=[a, b])
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107 return d
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108 elif isinstance(e, ir.Binop) and e.operation == '-' and \
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109 isinstance(e.b, ir.Const) and e.b.value < 8:
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110 a = self.munchExpr(e.a)
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111 d = self.newTmp()
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112 c = Imm3(e.b.value)
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113 self.emit(arm.subregregimm3_ins, others=[c], dst=[d], src=[a])
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114 return d
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115 elif isinstance(e, ir.Binop) and e.operation == '-':
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116 a = self.munchExpr(e.a)
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117 b = self.munchExpr(e.b)
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118 d = self.newTmp()
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119 self.emit(arm.subregs_ins, dst=[d], src=[a, b])
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120 return d
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121 elif isinstance(e, ir.Binop) and e.operation == '|':
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122 a = self.munchExpr(e.a)
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123 b = self.munchExpr(e.b)
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124 d = self.newTmp()
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125 self.move(d, a)
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126 self.emit(arm.orrregs_ins, dst=[], src=[b, d])
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127 return d
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128 elif isinstance(e, ir.Binop) and e.operation == '<<':
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129 a = self.munchExpr(e.a)
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130 b = self.munchExpr(e.b)
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131 d = self.newTmp()
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132 self.move(d, a)
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133 self.emit(arm.lslregs_ins, dst=[], src=[b, d]) # TODO: is d a source variable?
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134 return d
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135 elif isinstance(e, ir.Binop) and e.operation == '*':
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136 a = self.munchExpr(e.a)
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137 b = self.munchExpr(e.b)
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138 d = self.newTmp()
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139 self.move(d, a)
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140 # this mul instruction has operands swapped:
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141 self.emit(arm.mulregreg_ins, dst=[d], src=[b, d])
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142 return d
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143 elif isinstance(e, ir.Const) and e.value < 256:
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144 d = self.newTmp()
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145 self.emit(arm.mov_imm8_ins, others=[arm.Imm8(e.value)], dst=[d])
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146 return d
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147 elif isinstance(e, ir.Const) and e.value < (2**31):
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148 d = self.newTmp()
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149 ln = LabelRef(self.frame.addConstant(e.value))
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150 self.emit(arm.ldr_pcrel, others=[ln], dst=[d])
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151 return d
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152 elif isinstance(e, ir.Mem) and isinstance(e.e, ir.Binop) and \
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153 e.e.operation == '+' and isinstance(e.e.b, ir.Const):
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154 base = self.munchExpr(e.e.a)
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155 d = self.newTmp()
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156 c = e.e.b.value
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157 self.emit(arm.loadimm5_ins, others=[c], src=[base], dst=[d])
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158 return d
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159 elif isinstance(e, ir.Mem):
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160 # Load from memory
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161 base = self.munchExpr(e.e)
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162 d = self.newTmp()
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163 self.emit(arm.loadimm5_ins, others=[0], src=[base], dst=[d])
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164 return d
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165 elif isinstance(e, ir.Temp):
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166 return e
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167 elif isinstance(e, ir.Call):
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168 # Move arguments into proper locations:
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169 reguses = []
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170 for i, a in enumerate(e.arguments):
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171 loc = self.frame.argLoc(i)
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172 m = ir.Move(loc, a)
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173 self.munchStm(m)
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174 if isinstance(loc, ir.Temp):
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175 reguses.append(loc)
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176 self.emit(arm.bl_ins(LabelRef(e.f.name)), src=reguses, dst=[self.frame.rv])
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177 d = self.newTmp()
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178 self.move(d, self.frame.rv)
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179 return d
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180 else:
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181 raise NotImplementedError('Expr --> {}'.format(e))
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182
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183 def munchStm(self, s):
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184 if isinstance(s, ir.Terminator):
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185 pass
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186 elif isinstance(s, ir.Move) and isinstance(s.dst, ir.Mem) and \
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187 isinstance(s.dst.e, ir.Binop) and s.dst.e.operation == '+' and \
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188 isinstance(s.dst.e.b, ir.Const):
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189 a = self.munchExpr(s.dst.e.a)
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190 val = self.munchExpr(s.src)
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191 c = s.dst.e.b.value
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192 self.emit(arm.storeimm5_ins, others=[c], src=[a, val])
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193 elif isinstance(s, ir.Move) and isinstance(s.dst, ir.Mem):
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194 memloc = self.munchExpr(s.dst.e)
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195 val = self.munchExpr(s.src)
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196 self.emit(arm.storeimm5_ins, others=[0], src=[memloc, val])
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197 elif isinstance(s, ir.Move) and isinstance(s.dst, ir.Temp):
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198 val = self.munchExpr(s.src)
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199 dreg = s.dst
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200 self.move(dreg, val)
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201 elif isinstance(s, ir.Exp):
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202 # Generate expression code and discard the result.
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203 x = self.munchExpr(s.e)
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204 self.emit(Nop(), src=[x])
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205 elif isinstance(s, ir.Jump):
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206 tgt = self.targets[s.target]
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207 self.emit(arm.b_ins(LabelRef(s.target.name)), jumps=[tgt])
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208 elif isinstance(s, ir.CJump):
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209 a = self.munchExpr(s.a)
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210 b = self.munchExpr(s.b)
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211 self.emit(arm.cmp_ins, src=[a, b])
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212 ntgt = self.targets[s.lab_no]
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213 ytgt = self.targets[s.lab_yes]
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214 jmp_ins = makeIns(arm.b_ins(LabelRef(s.lab_no.name)), jumps=[ntgt])
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215 opnames = {'<': arm.blt_ins, '>':arm.bgt_ins, '==':arm.beq_ins}
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216 op = opnames[s.cond](LabelRef(s.lab_yes.name))
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217 self.emit(op, jumps=[ytgt, jmp_ins]) # Explicitely add fallthrough
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218 self.emit2(jmp_ins)
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219 else:
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220 raise NotImplementedError('Stmt --> {}'.format(s))
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221
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222 def move(self, dst, src):
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223 self.emit(arm.movregreg_ext_ins, src=[src], dst=[dst])
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224
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225
274
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226 # TODO: this class could be target independent:
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227 class ArmCodeGenerator:
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228 def __init__(self, outs):
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229 # TODO: schedule traces in better order.
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230 # This is optional!
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231 self.ins_sel = ArmInstructionSelector()
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232 self.ra = registerallocator.RegisterAllocator()
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233 self.outs = outs
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234 self.outs.getSection('code').address = 0x08000000
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235 self.outs.getSection('data').address = 0x20000000
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236
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237 def generateFunc(self, irfunc):
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238 """ Generate code for one function into a frame """
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239 # Cleanup function:
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240 transform.removeEmptyBlocks(irfunc)
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241
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242 # Create a frame for this function:
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243 frame = ArmFrame(irfunc.name)
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244
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245 # Canonicalize the intermediate language:
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246 canon.make(irfunc, frame)
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247 self.ins_sel.munchFunction(irfunc, frame)
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248
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249 # Do register allocation:
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250 self.ra.allocFrame(frame)
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251 # TODO: Peep-hole here?
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252
280
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253 # Can we materialize here??
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254
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255 # Add label and return and stack adjustment:
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256 frame.EntryExitGlue3()
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257
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258 # Materialize assembly
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259 # Materialize the register allocated instructions into a stream of
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260 # real instructions.
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261 frame.lower_to(self.outs)
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262 return frame
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263
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264 def generate(self, ircode):
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265 self.outs.selectSection('code')
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266 # assembly glue to make it work:
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267 # TODO: this must be in source code, not in compiler
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268 self.outs.emit(arm.dcd_ins(Imm32(0x20000678))) # initial SP
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269 self.outs.emit(arm.dcd_ins(Imm32(0x08000009))) # reset vector
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270 self.outs.emit(arm.b_ins(LabelRef('main')))
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271
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272 # Munch program into a bunch of frames. One frame per function.
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273 # Each frame has a flat list of abstract instructions.
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274 # Generate code for all functions:
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275 self.frames = [self.generateFunc(func) for func in ircode.Functions]
274
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276
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277 # TODO: fixup references, do this in another way?
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278 self.outs.backpatch()
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279 self.outs.backpatch()
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280 return self.frames
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281