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1 import logging
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2 import ir
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3 from target import Label, Comment, Alignment, LabelRef, Imm32, DebugInfo
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4 import cortexm3 as arm
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5 from ppci import CompilerError
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6
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7 class ArmCodeGenerator:
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8 """
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9 Simple code generator
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10 Ad hoc implementation
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11 """
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12 def __init__(self, out):
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13 self.outs = out
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14 self.logger = logging.getLogger('codegenarm')
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15
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16 def emit(self, item):
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17 self.outs.emit(item)
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18
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19 def generate(self, ircode):
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20 assert isinstance(ircode, ir.Module)
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21 self.logger.info('Generating arm code for {}'.format(ircode.name))
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22 self.available_regs = {arm.r2, arm.r3, arm.r4, arm.r5, arm.r6, arm.r7}
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23 self.regmap = {}
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24 # TODO: get these from linker descriptor?
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25 self.outs.getSection('code').address = 0x08000000
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26 self.outs.getSection('data').address = 0x20000000
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27 self.outs.selectSection('data')
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28
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29 for gvar in ircode.Variables:
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30 self.emit(Label(gvar.name))
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31 # TODO: use initial value:
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32 self.dcd(0)
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33
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34 self.imms = [] # list with immediates relative to PC.
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35 self.outs.selectSection('code')
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36
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37 # Manually inserted startup code:
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38 self.dcd(0x20000678) # initial stack ptr
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39 # TODO: use label here:
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40 #self.emit(arm.dcd_ins(LabelRef('reset'))) # reset vector
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41 self.dcd(0x08000009) # reset vector, lsb indicates thumb mode
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42
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43 self.emit(Label('reset'))
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44 for f in ircode.Functions:
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45 self.localVars = []
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46 # Add global variable addresses to immediate list:
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47 for gvar in ircode.Variables:
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48 pass #self.imms.append((
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49
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50 self.stack_frame = []
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51 self.emit(Label(f.name))
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52 # Save some registers:
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53 self.emit(arm.push_ins(arm.RegisterSet({arm.r4, arm.r5, arm.r6,arm.r7,arm.lr})))
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54 for bb in f.BasicBlocks:
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55 self.emit(Label(bb.name))
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56 for ins in bb.Instructions:
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57 self.generateInstruction(ins)
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58
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59 self.align()
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60 while self.imms:
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61 l, v = self.imms.pop()
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62 self.emit(Label(l))
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63 self.dcd(v)
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64 self.align()
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65 self.outs.backpatch()
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66 self.outs.backpatch()
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67 codesize = self.outs.getSection('code').Size
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68 self.logger.info('Generated {} bytes code'.format(codesize))
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69
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70 def dcd(self, x):
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71 self.emit(arm.dcd_ins(Imm32(x)))
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72
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73 def align(self):
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74 self.outs.emit(Alignment(4))
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75
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76 # Helper functions:
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77 def getStack(self, v):
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78 off = self.stack_frame.index(v)
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79 return off * 4
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80
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81 def addStack(self, v):
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82 self.stack_frame.append(v)
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83 return self.getStack(v)
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84
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85 def getGlobal(self, r, g):
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86 _global_address = g.name + '__global'
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87 self.emit(arm.ldr_pcrel(r, LabelRef(_global_address)))
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88
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89 def loadStack(self, reg, val):
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90 self.emit(arm.ldr_sprel(reg, arm.MemSpRel(self.getStack(val))))
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91
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92 def getreg(self, v):
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93 if not v in self.regmap:
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94 self.regmap[v] = self.available_regs.pop()
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95 return self.regmap[v]
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96
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97 def freereg(self, v, ins):
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98 if v.lastUse(ins):
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99 r = self.regmap.pop(v)
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100 assert r not in self.regmap.values()
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101 self.available_regs.add(r)
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102
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103 def comment(self, txt):
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104 self.emit(Comment(txt))
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105
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106 def debugInfo(self, loc):
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107 if loc:
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108 self.emit(DebugInfo(loc))
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109
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110 def generateInstruction(self, ins):
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111 self.comment(str(ins))
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112 if hasattr(ins, 'debugLoc'):
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113 self.debugInfo(ins.debugLoc)
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114 if type(ins) is ir.Branch:
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115 tgt = LabelRef(ins.target.name)
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116 self.emit(arm.b_ins(tgt))
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117 elif type(ins) is ir.ImmLoad:
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118 lname = ins.target.name + '_ivalue'
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119 r0 = self.getreg(ins.target)
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120 self.emit(arm.ldr_pcrel(r0, LabelRef(lname)))
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121 self.imms.append((lname, ins.value))
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122 elif type(ins) is ir.Store:
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123 # Load value in r0:
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124 r0 = self.getreg(ins.value)
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125 # store in memory:
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126 # TODO: split globals and locals??
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127 #self.getGlobal(arm.r1, ins.location)
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128 # Horrible hack with localVars
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129 if ins.location in self.localVars:
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130 # The value was alloc'ed
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131 self.emit(arm.str_sprel(r0, arm.MemSpRel(self.getStack(ins.location))))
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132 else:
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133 r1 = self.getreg(ins.location)
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134 self.emit(arm.storeimm5_ins(r0, arm.MemR8Rel(r1, 0)))
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135 self.freereg(ins.location, ins)
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136 self.freereg(ins.value, ins)
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137 elif type(ins) is ir.Load:
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138 # TODO: differ global and local??
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139 #self.getGlobal(arm.r0, ins.location)
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140 r0 = self.getreg(ins.value)
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141 if ins.location in self.localVars:
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142 self.emit(arm.ldr_sprel(r0, arm.MemSpRel(self.getStack(ins.location))))
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143 else:
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144 r2 = self.getreg(ins.location)
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145 self.emit(arm.loadimm5_ins(r0, arm.MemR8Rel(r2, 0)))
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146 self.freereg(ins.location, ins)
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147 elif type(ins) is ir.BinaryOperator:
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148 # Load operands:
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149 r0 = self.getreg(ins.value1)
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150 r1 = self.getreg(ins.value2)
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151 r2 = self.getreg(ins.result)
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152 # do operation:
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153 if ins.operation == '+':
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154 self.emit(arm.addregs_ins(r2, r0, r1))
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155 elif ins.operation == '<<':
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156 self.emit(arm.movregreg_ins(r2, r0))
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157 self.emit(arm.lslregs_ins(r2, r1))
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158 elif ins.operation == '|':
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159 self.emit(arm.movregreg_ins(r2, r0))
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160 self.emit(arm.orrregs_ins(r2, r1))
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161 else:
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162 raise NotImplementedError('operation {} not implemented'.format(ins.operation))
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163 self.freereg(ins.value1, ins)
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164 self.freereg(ins.value2, ins)
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165 elif type(ins) is ir.Return:
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166 self.emit(arm.pop_ins(arm.RegisterSet({arm.r4, arm.r5, arm.r6, arm.r7, arm.pc})))
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167 elif type(ins) is ir.ConditionalBranch:
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168 r0 = self.getreg(ins.a)
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169 r1 = self.getreg(ins.b)
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170 self.emit(arm.cmp_ins(r1, r0))
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171 tgt_yes = Label(ins.lab1.name)
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172 if ins.cond == '==':
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173 self.emit(arm.beq_ins(tgt_yes))
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174 else:
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175 raise NotImplementedError('"{}" not covered'.format(ins.cond))
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176 tgt_no = Label(ins.lab2.name)
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177 self.emit(arm.jmp_ins(tgt_no))
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178 self.freereg(ins.a, ins)
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179 self.freereg(ins.b, ins)
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180 elif type(ins) is ir.Alloc:
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181 # Local variables are added to stack
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182 self.addStack(ins.value)
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183 self.localVars.append(ins.value)
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184 # load address into variable:
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185 else:
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186 raise NotImplementedError('IR "{}" not covered'.format(ins))
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187
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