|
340
|
1
|
|
375
|
2
|
|
|
3 interrupt_vector_table:
|
|
|
4 ivt_reset: B start ; 0x0 reset
|
|
|
5 ivt_undef: B undef_handler ; 0x4 undefined instruction
|
|
|
6 ivt_svc: B undef_handler ; 0x08 Supervisor call
|
|
|
7 ivt_prefetch: B undef_handler ; 0x0C prefetch abort
|
|
|
8 ivt_data: B undef_handler ; 0x10 data abort
|
|
|
9 ivt_hyptrap: B undef_handler ; 0x14 not used
|
|
|
10 ivt_irq: B undef_handler ; 0x18 IRQ
|
|
|
11 ivt_fiq: B undef_handler ; 0x18 FIQ
|
|
|
12
|
|
|
13
|
|
|
14 start:
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|
|
15
|
|
|
16 ; Setup TTBR1 (translation table base register)
|
|
|
17
|
|
377
|
18 ; mov r0, =kernel_table0-KERNEL_BASE
|
|
375
|
19 mcr p15, 0, r0, c2, c0, 1 ; TTBR1
|
|
|
20 mcr p15, 0, r0, c2, c0, 0 ; TTBR0
|
|
|
21
|
|
|
22 ; Prepare the TTBCR (translation table base control register)
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|
|
23 mov r0, 0x1 ; TBD: why set this to 1?
|
|
|
24 mcr p15, 0, r0, c2, c0, 2
|
|
|
25
|
|
|
26 ; Enable the VMSA (Virtual memory system architecture):
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|
|
27 mrc p15, 0, r0, c1, c0, 0
|
|
|
28 ; TODO:
|
|
|
29 ; orr r0, r0, 0x1
|
|
|
30 mcr p15, 0, r0, c1, c0, 0
|
|
|
31
|
|
|
32 ; Setup stack:
|
|
352
|
33 mov sp, 0x30000
|
|
|
34 BL kernel_start ; Branch to main (this is actually in the interrupt vector)
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|
|
35 local_loop:
|
|
|
36 B local_loop
|
|
362
|
37
|
|
|
38
|
|
375
|
39 ; Interrupt handlers:
|
|
|
40
|
|
|
41 undef_handler:
|
|
|
42 B undef_handler
|
|
|
43
|
|
362
|
44 ; Called to identify the proc:
|
|
367
|
45 archmem_pfr0:
|
|
362
|
46 mrc p15, 0, r0, c0, c1, 0
|
|
|
47 mov pc, lr
|
|
|
48
|
|
367
|
49 archmem_pfr1:
|
|
362
|
50 mrc p15, 0, r0, c0, c1, 1
|
|
|
51 mov pc, lr
|
|
|
52
|
|
367
|
53 archmem_mmfr0:
|
|
362
|
54 mrc p15, 0, r0, c0, c1, 4
|
|
|
55 mov pc, lr
|
|
|
56
|
|
|
57
|
|
367
|
58 archmem_mpuir:
|
|
362
|
59 mrc p15, 0, r0, c0, c0, 4
|
|
|
60 mov pc, lr
|
