interrupt_vector_table:
ivt_reset: B start  ; 0x0 reset
ivt_undef: B undef_handler  ; 0x4 undefined instruction
ivt_svc: B undef_handler  ; 0x08 Supervisor call
ivt_prefetch: B undef_handler ; 0x0C prefetch abort
ivt_data: B undef_handler  ; 0x10 data abort
ivt_hyptrap: B undef_handler ; 0x14 not used
ivt_irq: B undef_handler  ; 0x18 IRQ
ivt_fiq: B undef_handler  ; 0x18 FIQ


start:

; Setup TTBR1 (translation table base register)

mov r0, 0
mcr p15, 0, r0, c2, c0, 1 ; TTBR1
mcr p15, 0, r0, c2, c0, 0 ; TTBR0

; Prepare the TTBCR (translation table base control register)
mov r0, 0x1  ; TBD: why set this to 1?
mcr p15, 0, r0, c2, c0, 2

; Enable the VMSA (Virtual memory system architecture):
mrc p15, 0, r0, c1, c0, 0
; TODO:
; orr r0, r0, 0x1
mcr p15, 0, r0, c1, c0, 0

; Setup stack:
mov sp, 0x30000
BL kernel_start          ; Branch to main (this is actually in the interrupt vector)
local_loop:
B local_loop


; Interrupt handlers:

undef_handler:
B undef_handler

; Called to identify the proc:
archmem_pfr0:
mrc p15, 0, r0, c0, c1, 0
mov pc, lr

archmem_pfr1:
mrc p15, 0, r0, c0, c1, 1
mov pc, lr

archmem_mmfr0:
mrc p15, 0, r0, c0, c1, 4
mov pc, lr


archmem_mpuir:
mrc p15, 0, r0, c0, c0, 4
mov pc, lr