annotate python/ppci/target/thumb/armtarget.py @ 393:6ae782a085e0

Added init program
author Windel Bouwman
date Sat, 17 May 2014 21:17:40 +0200
parents 6df89163e114
children
rev   line source
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1 import struct
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2 from ..basetarget import Register, Instruction, Target, Label, Alignment
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3 from .instructions import Add2, Sub, Sub3, Add3, Cmp, Lsl, Orr, Add, Cmp2, Sub2, Add2, Mul, And
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4 from .instructions import Dcd, Pop, Push, Yield, Mov2, Mov3
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5 from .instructions import B, Bl, Bne, Beq, Blt, Bgt
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6 from .instructions import Ldr, Str2, Ldr2, Str1, Ldr1, Ldr3
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7
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8 from .frame import ArmFrame
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9 from .arminstructionselector import ArmInstructionSelector
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10 from ..arm.registers import R0, R1, R2, R3, R4, R5, R6, R7, SP, LR, PC
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11 from ..arm.registers import register_range
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12 from ...assembler import BaseAssembler
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13
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14
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15 """ ARM target description. """
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16
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17 # TODO: encode this in DSL (domain specific language)
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18 # TBD: is this required?
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19 # TODO: make a difference between armv7 and armv5?
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20
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21
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22 class ThumbAssembler(BaseAssembler):
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23 def __init__(self, target):
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24 super().__init__(target)
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25 self.make_parser()
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26
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27
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28 class ThumbTarget(Target):
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29 def __init__(self):
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30 super().__init__('thumb')
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31 self.ins_sel = ArmInstructionSelector()
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32 self.FrameClass = ArmFrame
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33 self.add_rules()
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34
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35 # Add lowering options:
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36 self.add_lowering(Str2, lambda im: Str2(im.src[1], im.src[0], im.others[0]))
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37 self.add_lowering(Ldr2, lambda im: Ldr2(im.dst[0], im.src[0], im.others[0]))
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38 self.add_lowering(Ldr3, lambda im: Ldr3(im.dst[0], im.others[0]))
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39 self.add_lowering(Mov3, lambda im: Mov3(im.dst[0], im.others[0]))
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40 self.add_lowering(Add2, lambda im: Add2(im.dst[0], im.src[0], im.others[0]))
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41 self.add_lowering(Sub2, lambda im: Sub2(im.dst[0], im.src[0], im.others[0]))
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42 self.add_lowering(Mov2, lambda im: Mov2(im.dst[0], im.src[0]))
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43 self.add_lowering(Add3, lambda im: Add3(im.dst[0], im.src[0], im.src[1]))
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44 self.add_lowering(Sub3, lambda im: Sub3(im.dst[0], im.src[0], im.src[1]))
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45 self.add_lowering(Mul, lambda im: Mul(im.src[0], im.dst[0]))
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46 self.add_lowering(And, lambda im: And(im.src[0], im.src[1]))
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47 self.add_lowering(Orr, lambda im: Orr(im.src[0], im.src[1]))
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48 self.add_lowering(Lsl, lambda im: Lsl(im.src[0], im.src[1]))
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49 self.add_lowering(Cmp, lambda im: Cmp(im.src[0], im.src[1]))
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50
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51 self.assembler = ThumbAssembler(self)
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52
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53 def add_rules(self):
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54
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55 # Add instructions:
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56 self.add_keyword('dcd')
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57 self.add_instruction(['dcd', 'imm32'], lambda rhs: Dcd(rhs[1]))
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58
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59 self.add_keyword('mov')
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60 self.add_instruction(['mov', 'reg8', ',', 'reg8'],
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61 lambda rhs: Mov2(rhs[1], rhs[3]))
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62
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63 self.add_instruction(['mov', 'reg8', ',', 'imm8'],
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64 lambda rhs: Mov3(rhs[1], rhs[3]))
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65
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66 self.add_keyword('add')
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67 self.add_instruction(['add', 'reg8', ',', 'reg8', ',', 'imm3'],
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68 lambda rhs: Add2(rhs[1], rhs[3], rhs[5]))
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69
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70 self.add_instruction(['add', 'reg8', ',', 'reg8', ',', 'reg8'],
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71 lambda rhs: Add3(rhs[1], rhs[3], rhs[5]))
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72
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73 self.add_keyword('sub')
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74 self.add_instruction(['sub', 'reg8', ',', 'reg8', ',', 'imm3'],
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75 lambda rhs: Sub(rhs[1], rhs[3], rhs[5]))
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76
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77 self.add_instruction(['sub', 'sp', ',', 'sp', ',', 'imm8'],
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78 lambda rhs: Sub(SP, SP, rhs[5]))
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79
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80 self.add_instruction(['add', 'sp', ',', 'sp', ',', 'imm8'],
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81 lambda rhs: Add(SP, SP, rhs[5]))
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82
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83 self.add_keyword('cmp')
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84 self.add_instruction(['cmp', 'reg8', ',', 'reg8'],
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85 lambda rhs: Cmp(rhs[1], rhs[3]))
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86 self.add_instruction(['cmp', 'reg8', ',', 'imm8'],
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87 lambda rhs: Cmp2(rhs[1], rhs[3]))
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88
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89 self.add_keyword('lsl')
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90 self.add_instruction(['lsl', 'reg8', ',', 'reg8'],
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91 lambda rhs: Lsl(rhs[1], rhs[3]))
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92
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93 self.add_keyword('str')
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94 self.add_instruction(['str', 'reg8', ',', '[', 'reg8', '+', 'imm5', ']'],
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95 lambda rhs: Str2(rhs[1], rhs[4], rhs[6]))
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96
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97 self.add_keyword('ldr')
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98 self.add_instruction(['ldr', 'reg8', ',', '[', 'reg8', '+', 'imm5', ']'],
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99 lambda rhs: Ldr2(rhs[1], rhs[4], rhs[6]))
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100
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101 self.add_instruction(['str', 'reg8', ',', '[', 'sp', '+', 'imm8', ']'],
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102 lambda rhs: Str1(rhs[1], rhs[6]))
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103
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104 self.add_instruction(['ldr', 'reg8', ',', '[', 'sp', '+', 'imm8', ']'],
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105 lambda rhs: Ldr1(rhs[1], rhs[6]))
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106
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107 self.add_keyword('pop')
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108 self.add_instruction(['pop', 'reg_list'], lambda rhs: Pop(rhs[1]))
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109 self.add_keyword('push')
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110 self.add_instruction(['push', 'reg_list'], lambda rhs: Push(rhs[1]))
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111
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112 self.add_keyword('yield')
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113 self.add_instruction(['yield'], lambda rhs: Yield())
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114
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115 self.add_keyword('b')
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116 self.add_keyword('bl')
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117 self.add_instruction(['b', 'ID'], lambda rhs: B(rhs[1].val))
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118 self.add_instruction(['bl', 'ID'], lambda rhs: Bl(rhs[1].val))
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119 self.add_keyword('beq')
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120 self.add_keyword('bne')
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121 self.add_keyword('blt')
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122 self.add_keyword('bgt')
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123 self.add_instruction(['beq', 'ID'], lambda rhs: Beq(rhs[1].val))
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124 self.add_instruction(['bne', 'ID'], lambda rhs: Bne(rhs[1].val))
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125 self.add_instruction(['blt', 'ID'], lambda rhs: Blt(rhs[1].val))
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126 self.add_instruction(['bgt', 'ID'], lambda rhs: Bgt(rhs[1].val))
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127
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128 self.add_keyword('align')
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129 self.add_instruction(['align', 'imm8'], lambda rhs: Alignment(rhs[1]))
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130
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131 self.add_instruction(['ldr', 'reg8', ',', 'ID'],
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132 lambda rhs: Ldr(rhs[1], rhs[3].val))
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133
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134 # Additional rules:
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135
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136 # Register list grammar:
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137 self.add_rule('reg_list', ['{', 'reg_list_inner', '}'],
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138 lambda rhs: rhs[1])
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139 self.add_rule('reg_list_inner', ['reg_or_range'],
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140 lambda rhs: rhs[0])
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141 self.add_rule('reg_list_inner', ['reg_or_range', ',', 'reg_list_inner'],
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142 lambda rhs: rhs[0] | rhs[2])
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143 self.add_rule('reg_or_range', ['reg8'], lambda rhs: {rhs[0]})
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144 self.add_rule('reg_or_range', ['lr'], lambda rhs: {LR})
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145 self.add_rule('reg_or_range', ['pc'], lambda rhs: {PC})
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146
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147 self.add_rule('reg_or_range', ['reg8', '-', 'reg8'],
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148 lambda rhs: register_range(rhs[0], rhs[2]))
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149
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150 self.add_keyword('r0')
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151 self.add_keyword('r1')
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152 self.add_keyword('r2')
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153 self.add_keyword('r3')
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154 self.add_keyword('r4')
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155 self.add_keyword('r5')
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156 self.add_keyword('r6')
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157 self.add_keyword('r7')
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158 self.add_keyword('sp')
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159 self.add_keyword('lr')
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160 self.add_keyword('pc')
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161 self.add_rule('reg8', ['r0'], lambda rhs: R0)
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162 self.add_rule('reg8', ['r1'], lambda rhs: R1)
4d204f6f7d4e Rewrite of assembler parts
Windel Bouwman
parents: 340
diff changeset
163 self.add_rule('reg8', ['r2'], lambda rhs: R2)
4d204f6f7d4e Rewrite of assembler parts
Windel Bouwman
parents: 340
diff changeset
164 self.add_rule('reg8', ['r3'], lambda rhs: R3)
4d204f6f7d4e Rewrite of assembler parts
Windel Bouwman
parents: 340
diff changeset
165 self.add_rule('reg8', ['r4'], lambda rhs: R4)
4d204f6f7d4e Rewrite of assembler parts
Windel Bouwman
parents: 340
diff changeset
166 self.add_rule('reg8', ['r5'], lambda rhs: R5)
4d204f6f7d4e Rewrite of assembler parts
Windel Bouwman
parents: 340
diff changeset
167 self.add_rule('reg8', ['r6'], lambda rhs: R6)
4d204f6f7d4e Rewrite of assembler parts
Windel Bouwman
parents: 340
diff changeset
168 self.add_rule('reg8', ['r7'], lambda rhs: R7)
4d204f6f7d4e Rewrite of assembler parts
Windel Bouwman
parents: 340
diff changeset
169