annotate python/target/armtarget.py @ 292:534b94b40aa8

Fixup reorganize
author Windel Bouwman
date Wed, 27 Nov 2013 08:06:42 +0100
parents 7b38782ed496
children 44f336460c2a
rev   line source
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444b9df2ed99 try to split up code generation
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1 import struct
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2 from .basetarget import Register, Instruction, Target, Label, LabelRef
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3 from .basetarget import Imm32, Imm8, Imm7, Imm3
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4 from .arminstructions import allins, Reg8Op, ArmRegister
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5 from .arminstructions import Dcd, B
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6 from .arminstructions import R0, R1, R2, R3, R4, R5, R6, R7, LR, PC, SP
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f22b431f4113 Added arm add instruction
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7
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8
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9 """ ARM target description. """
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10
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11 # TODO: encode this in DSL (domain specific language)
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12 # TBD: is this required?
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13 # TODO: make a difference between armv7 and armv5?
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1fa3e0050b49 Expanded ad hoc code generator
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14
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046017431c6a Started register allocator
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15
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16 class ArmTarget(Target):
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17 def __init__(self):
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18 super().__init__('arm')
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19 for i in allins:
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20 self.addInstruction(i)
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21 # TODO: fix this nicer?
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22 #setattr(self, i.__name__, i)
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23 self.check()
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24
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25 def startCode(self, outs):
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26 """ Emit some startup code in the output stream """
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27 outs.selectSection('code')
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28 # assembly glue to make it work:
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29 # TODO: this must be in source code, not in compiler
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30 outs.emit(Dcd(Imm32(0x20000678))) # initial SP
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31 outs.emit(Dcd(Imm32(0x08000009))) # reset vector
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32 outs.emit(B(LabelRef('main')))