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1 #!/usr/bin/python
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2
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199
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3 import unittest, cProfile
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200
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4 from ppci import CompilerError
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201
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5 from asmnodes import AInstruction, ABinop, AUnop, ASymbol, ALabel, ANumber
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6 from asm import tokenize, Assembler
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199
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7 import msp430
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8 import cortexm3 as arm
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9
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198
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10 class AssemblerLexingCase(unittest.TestCase):
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11 """ Tests the assemblers lexer """
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12
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13 def testLex0(self):
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14 """ Check if the lexer is OK """
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15 asmline, toks = 'mov rax, rbx ', ['ID', 'ID', ',', 'ID']
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16 self.assertSequenceEqual([tok.typ for tok in tokenize(asmline)], toks)
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17
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18 def testLex1(self):
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19 """ Test if lexer correctly maps some tokens """
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20 asmline, toks = 'lab1: mov rax, rbx ', ['ID', ':', 'ID', 'ID', ',', 'ID']
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21 self.assertSequenceEqual([tok.typ for tok in tokenize(asmline)], toks)
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22
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23 def testLex1(self):
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24 """ Test if lexer correctly maps some tokens """
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25 asmline, toks = 'mov 3.13 0xC 13', ['ID', 'REAL', 'NUMBER', 'NUMBER']
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26 self.assertSequenceEqual([tok.typ for tok in tokenize(asmline)], toks)
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27
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28 def testLex2(self):
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29 """ Test if lexer fails on a token that is invalid """
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30 asmline = '0z4: mov rax, rbx $ '
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31 with self.assertRaises(CompilerError):
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32 list(tokenize(asmline))
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33
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34 class AssemblerParsingTestCase(unittest.TestCase):
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35 """
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36 Tests the assembler parts
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37 """
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38 def setUp(self):
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39 self.a = Assembler()
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40
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41 def testParse(self):
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42 asmline = 'lab1: mov rax, rbx'
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43 self.a.parse_line(asmline)
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44
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45 def testParse2(self):
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46 asmline = 'a: mov rax, [rbx + 2]'
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47 self.a.parse_line(asmline)
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48 output = []
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49 output.append(ALabel('a'))
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50 output.append(AInstruction('mov', [ASymbol('rax'), AUnop('[]', ASymbol('rbx') + ANumber(2))]))
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51 self.assertSequenceEqual(output, self.a.output)
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52
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53 def testParse3(self):
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54 # A label must be optional:
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55 asmline = 'mov rax, 1'
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56 self.a.parse_line(asmline)
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57 output = [AInstruction('mov', [ASymbol('rax'), ANumber(1)])]
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58 self.assertSequenceEqual(output, self.a.output)
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59
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60 def testParse4(self):
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61 # Test 3 operands:
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62 asmline = 'add rax, [4*rbx + 22], rcx'
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63 self.a.parse_line(asmline)
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64 ops = []
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65 ops.append(ASymbol('rax'))
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66 ops.append(AUnop('[]', ANumber(4) * ASymbol('rbx') + ANumber(22)))
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67 ops.append(ASymbol('rcx'))
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68 output = [AInstruction('add', ops)]
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69 self.assertSequenceEqual(output, self.a.output)
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70
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71 def testParse5(self):
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72 # An instruction must be optional:
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73 asmline = 'lab1:'
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74 self.a.parse_line(asmline)
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75 output = []
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76 output.append(ALabel('lab1'))
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77 self.assertSequenceEqual(output, self.a.output)
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78
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79 def testParse6(self):
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80 # A line can be empty
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81 self.a.parse_line('')
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82
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83 class AssemblerOtherTestCase(unittest.TestCase):
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84 def testWithoutTarget(self):
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85 a = Assembler()
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86 with self.assertRaises(CompilerError):
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87 a.assemble_line('')
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88
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89 @unittest.skip
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90 def testX86(self):
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91 testsrc = """ ; tst
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92 begin:
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93 mov rax, rbx ; 0x48, 0x89, 0xd8
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94 xor rcx, rbx ; 0x48, 0x31, 0xd9
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95 inc rcx ; 0x48 0xff 0xc1
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96 """
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97 a = Assembler()
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98 a.assemble(testsrc)
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99 # Compare with nasm output:
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100 nasmbytes = [0x48, 0x89, 0xd8, 0x48, 0x31, 0xd9, 0x48, 0xff, 0xc1]
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101
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102 class AssemblerMSP430TestCase(unittest.TestCase):
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103 def setUp(self):
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104 self.t = msp430.msp430target
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105 self.a = Assembler(target=self.t)
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106
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107 def testMapMovInstruction(self):
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108 i = AInstruction('mov', [ASymbol('r14'), ASymbol('r15')])
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109 ri = self.t.mapInstruction(i)
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110
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111 def testMapRetiInstruction(self):
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112 i = AInstruction('reti', [])
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113 ri = self.t.mapInstruction(i)
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114
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115 @unittest.skip
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116 def testMapOperand(self):
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117 o = ASymbol('r14')
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118 mo = self.t.mapOperand(o)
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119 self.assertEqual(mo, msp430.r14)
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120
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121 @unittest.skip
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122 def testMapOperandIndirection(self):
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123 o = AUnop('[]', ASymbol('r14'))
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124 mo = self.t.mapOperand(o)
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125
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126 def testMov(self):
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127 line1 = "mov r14, r15"
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128 self.a.assemble_line(line1)
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129 self.assertEqual(bytes([0x0F, 0x4E]), self.a.binout)
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130
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131 def testMov1337(self):
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132 line1 = "mov 0x1337, r12"
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133 self.a.assemble_line(line1)
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134 self.assertEqual(bytes.fromhex('3C403713'), self.a.binout)
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135
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136 def testAdd(self):
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137 line1 = "add r15, r13"
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138 self.a.assemble_line(line1)
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139 self.assertEqual(bytes.fromhex('0D5F'), self.a.binout)
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140
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141 def testReti(self):
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142 line1 = "reti"
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143 self.a.assemble_line(line1)
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144 self.assertEqual(bytes([0x0, 0x13]), self.a.binout)
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145
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146 def testMSPinstructionCount(self):
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147 """ Check that there are 27 instructions """
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148 self.assertEqual(27, len(self.t.instructions))
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149
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150
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151 class AssemblerARMTestCase(unittest.TestCase):
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152 def setUp(self):
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153 self.t = arm.armtarget
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154 self.a = Assembler(target=self.t)
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155
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156 def feed(self, line):
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157 self.a.assemble(line)
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158
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159 def check(self, hexstr):
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160 self.assertSequenceEqual(bytes.fromhex(hexstr), self.a.binout)
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161
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162 def testMapOperand(self):
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163 pass
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164
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165 def testMovImm8(self):
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166 self.feed('mov r4, 100')
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167 self.check('6424')
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168
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169 def testYield(self):
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170 self.feed('yield')
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171 self.check('10bf')
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172
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173 def testPush(self):
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174 self.feed('push {r2,r3,lr}')
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175 self.check('0cb5')
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176
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177 def testPop(self):
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178 self.feed('pop {r4-r6, pc}')
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179 self.check('70bd')
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180
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181 def testStr5(self):
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182 self.feed('str r4, [r1 + 0]')
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183 self.check('0c60')
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184
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185 def testLdr5(self):
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186 self.feed('ldr r4, [r0 + 0]')
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187 self.check('0468')
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188
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189 def testCmpRegReg(self):
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190 self.feed('cmp r0, r1')
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191 self.check('8842')
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192
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193 def testSequence1(self):
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194 self.feed('mov r5, 3')
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195 self.feed('add r4, r5, 0')
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196 self.feed('loop: add r6, r4, 7')
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197 self.feed('cmp r6, 5')
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198 self.check('0325 2c1c e61d 052e')
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200 if __name__ == '__main__':
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203
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201 #cProfile.run('unittest.main()')
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202 unittest.main()
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