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1 #!/usr/bin/python
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2
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3 import unittest, cProfile
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4 from ppci import CompilerError
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5 from asmnodes import AInstruction, ABinop, AUnop, ASymbol, ALabel, ANumber
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6 from asm import tokenize, Assembler
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7 import msp430
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8
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9 class AssemblerLexingCase(unittest.TestCase):
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10 """ Tests the assemblers lexer """
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11
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12 def testLex0(self):
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13 """ Check if the lexer is OK """
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14 asmline, toks = 'mov rax, rbx ', ['ID', 'ID', ',', 'ID']
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15 self.assertSequenceEqual([tok.typ for tok in tokenize(asmline)], toks)
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16
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17 def testLex1(self):
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18 """ Test if lexer correctly maps some tokens """
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19 asmline, toks = 'lab1: mov rax, rbx ', ['ID', ':', 'ID', 'ID', ',', 'ID']
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20 self.assertSequenceEqual([tok.typ for tok in tokenize(asmline)], toks)
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21
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22 def testLex1(self):
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23 """ Test if lexer correctly maps some tokens """
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24 asmline, toks = 'mov 3.13 0xC 13', ['ID', 'REAL', 'NUMBER', 'NUMBER']
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25 self.assertSequenceEqual([tok.typ for tok in tokenize(asmline)], toks)
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26
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27 def testLex2(self):
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28 """ Test if lexer fails on a token that is invalid """
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29 asmline = '0z4: mov rax, rbx $ '
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30 with self.assertRaises(CompilerError):
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31 list(tokenize(asmline))
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32
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33 class AssemblerParsingTestCase(unittest.TestCase):
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34 """
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35 Tests the assembler parts
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36 """
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37 def setUp(self):
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38 self.a = Assembler()
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39
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40 def testParse(self):
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41 asmline = 'lab1: mov rax, rbx'
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42 self.a.parse_line(asmline)
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43
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44 def testParse2(self):
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45 asmline = 'a: mov rax, [rbx + 2]'
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46 self.a.parse_line(asmline)
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47 output = []
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48 output.append(ALabel('a'))
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49 output.append(AInstruction('mov', [ASymbol('rax'), AUnop('[]', ASymbol('rbx') + ANumber(2))]))
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50 self.assertSequenceEqual(output, self.a.output)
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51
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52 def testParse3(self):
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53 # A label must be optional:
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54 asmline = 'mov rax, 1'
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55 self.a.parse_line(asmline)
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56 output = [AInstruction('mov', [ASymbol('rax'), ANumber(1)])]
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57 self.assertSequenceEqual(output, self.a.output)
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58
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59 def testParse4(self):
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60 # Test 3 operands:
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61 asmline = 'add rax, [4*rbx + 22], rcx'
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62 self.a.parse_line(asmline)
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63 ops = []
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64 ops.append(ASymbol('rax'))
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65 ops.append(AUnop('[]', ANumber(4) * ASymbol('rbx') + ANumber(22)))
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66 ops.append(ASymbol('rcx'))
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67 output = [AInstruction('add', ops)]
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68 self.assertSequenceEqual(output, self.a.output)
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69
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70 def testParse5(self):
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71 # An instruction must be optional:
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72 asmline = 'lab1:'
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73 self.a.parse_line(asmline)
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74 output = []
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75 output.append(ALabel('lab1'))
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76 self.assertSequenceEqual(output, self.a.output)
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77
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78 def testParse6(self):
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79 # A line can be empty
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80 self.a.parse_line('')
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81
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82 class AssemblerOtherTestCase(unittest.TestCase):
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83 def testWithoutTarget(self):
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84 a = Assembler()
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85 with self.assertRaises(CompilerError):
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86 a.assemble_line('')
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87
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88 @unittest.skip
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89 def testX86(self):
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90 testsrc = """ ; tst
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91 begin:
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92 mov rax, rbx ; 0x48, 0x89, 0xd8
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93 xor rcx, rbx ; 0x48, 0x31, 0xd9
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94 inc rcx ; 0x48 0xff 0xc1
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95 """
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96 a = Assembler()
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97 a.assemble(testsrc)
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98 # Compare with nasm output:
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99 nasmbytes = [0x48, 0x89, 0xd8, 0x48, 0x31, 0xd9, 0x48, 0xff, 0xc1]
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100
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101 class AssemblerMSP430TestCase(unittest.TestCase):
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102 def setUp(self):
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103 self.t = msp430.msp430target
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104 self.a = Assembler(target=self.t)
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105
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106 def testMapMovInstruction(self):
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107 i = AInstruction('mov', [ASymbol('r14'), ASymbol('r15')])
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108 ri = self.t.mapInstruction(i)
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109
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110 def testMapRetiInstruction(self):
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111 i = AInstruction('reti', [])
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112 ri = self.t.mapInstruction(i)
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113
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114 @unittest.skip
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115 def testMapOperand(self):
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116 o = ASymbol('r14')
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117 mo = self.t.mapOperand(o)
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118 self.assertEqual(mo, msp430.r14)
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119
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120 @unittest.skip
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121 def testMapOperandIndirection(self):
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122 o = AUnop('[]', ASymbol('r14'))
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123 mo = self.t.mapOperand(o)
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124
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125 def testMov(self):
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126 line1 = "mov r14, r15"
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127 self.a.assemble_line(line1)
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128 self.assertEqual(bytes([0x0F, 0x4E]), self.a.binout)
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129
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130 def testMov1337(self):
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131 line1 = "mov 0x1337, r12"
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132 self.a.assemble_line(line1)
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133 self.assertEqual(bytes([0x3C, 0x40, 0x37, 0x13]), self.a.binout)
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134
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135 def testAdd(self):
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136 line1 = "add r15, r13"
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137 self.a.assemble_line(line1)
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138 self.assertEqual(bytes([0x0D, 0x5F]), self.a.binout)
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139
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140 def testReti(self):
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141 line1 = "reti"
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142 self.a.assemble_line(line1)
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143 self.assertEqual(bytes([0x0, 0x13]), self.a.binout)
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144
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145 def testMSPinstructionCount(self):
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146 """ Check that there are 27 instructions """
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147 self.assertEqual(27, len(self.t.instructions))
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148
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150 if __name__ == '__main__':
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151 # cProfile.run('unittest.main()')
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152 unittest.main()
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