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14
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1 ; The default interrupt handlers.
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2 ; from 20 - 31 are reserved vectors.
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3 ; below are the custom ones!
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4
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5 section .text
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6 align 4
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7
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25
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8 ; Function to read the current instruction pointer value:
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9 global read_rip
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10 read_rip:
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11 pop rax
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12 jmp rax
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13
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14
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14 global loadIDT
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15 loadIDT:
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17
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16 extern idtP
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17 ; TODO: make this pointer thing more insightfull:
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18 lidt [idtP]
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14
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19 ret
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20
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31
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21 ; ISR related assembler wrappers:
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22
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23 %macro ISR_NOERRCODE 1
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24 global INT%1
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25 INT%1:
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26 cli
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27 push strict qword 0 ; push dummy error code
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28 push strict qword %1 ; push interrupt number
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29 jmp isr_common_stub
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30 %endmacro
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31
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32 %macro ISR_ERRCODE 1
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33 global INT%1
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34 INT%1:
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35 cli
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36 push strict qword %1 ; push interrupt number
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37 jmp isr_common_stub
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38 %endmacro
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39
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40 isr_common_stub:
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41 ; Do some saving:
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17
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42 push rax
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43 push rcx
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44 push rdx
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45 push rbx
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46 push rbp
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47 push rsi
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48 push rdi
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31
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49
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50 ; AMD64 calling convention, first parameter is in rdi:
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51 mov rdi, rsp ; Load stack pointer into rdi to indicate where the registers on the stack are (so that we can change them!)
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17
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52
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31
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53 extern isr_handler
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54 call isr_handler
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55
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17
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56 pop rdi
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57 pop rsi
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58 pop rbp
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59 pop rbx
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60 pop rdx
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61 pop rcx
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62 pop rax
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63
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31
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64 add rsp, 16 ; cleanup error code and isr number
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65 sti
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66 iretq
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14
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67
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68 ; Exception handlers:
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31
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69 ISR_NOERRCODE 0
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70 ISR_NOERRCODE 1
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71 ISR_NOERRCODE 2
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72 ISR_NOERRCODE 3
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73 ISR_NOERRCODE 4
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74 ISR_NOERRCODE 5
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75 ISR_NOERRCODE 6
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76 ISR_NOERRCODE 7
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77 ISR_ERRCODE 8
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78 ISR_NOERRCODE 9
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79 ISR_ERRCODE 10
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80 ISR_ERRCODE 11
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81 ISR_ERRCODE 12
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82 ISR_ERRCODE 13
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83 ISR_ERRCODE 14
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84 ; 15 is reserved
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85 ISR_NOERRCODE 16
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86 ISR_ERRCODE 17
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87 ISR_NOERRCODE 18
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88 ISR_NOERRCODE 19
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14
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89
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31
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90 ISR_NOERRCODE 32
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91 ISR_NOERRCODE 33
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92 ISR_NOERRCODE 34
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14
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93
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31
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94 ; default handler:
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95 ISR_NOERRCODE 255
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96
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97
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