; The default interrupt handlers.
; from 20 - 31 are reserved vectors.
; below are the custom ones!

section .text
align 4

; Function to read the current instruction pointer value:
global read_rip
read_rip:
   pop rax
   jmp rax

global loadIDT
loadIDT:
  extern idtP
  ; TODO: make this pointer thing more insightfull:
  lidt [idtP]
  ret

; ISR related assembler wrappers:

%macro ISR_NOERRCODE 1
global INT%1
INT%1:
  cli
  push strict qword 0 ; push dummy error code
  push strict qword %1 ; push interrupt number
  jmp isr_common_stub
%endmacro

%macro ISR_ERRCODE 1
global INT%1
INT%1:
  cli
  push strict qword %1 ; push interrupt number
  jmp isr_common_stub
%endmacro

isr_common_stub:
  ; Do some saving:
  push rax
  push rcx
  push rdx
  push rbx
  push rbp
  push rsi
  push rdi

  ; AMD64 calling convention, first parameter is in rdi:
  mov rdi, rsp ; Load stack pointer into rdi to indicate where the registers on the stack are (so that we can change them!)

  extern isr_handler
  call isr_handler

  pop rdi
  pop rsi
  pop rbp
  pop rbx
  pop rdx
  pop rcx
  pop rax

  add rsp, 16 ; cleanup error code and isr number
  sti
  iretq

; Exception handlers:
ISR_NOERRCODE 0
ISR_NOERRCODE 1
ISR_NOERRCODE 2
ISR_NOERRCODE 3
ISR_NOERRCODE 4
ISR_NOERRCODE 5
ISR_NOERRCODE 6
ISR_NOERRCODE 7
ISR_ERRCODE   8
ISR_NOERRCODE 9
ISR_ERRCODE 10
ISR_ERRCODE 11
ISR_ERRCODE 12
ISR_ERRCODE 13
ISR_ERRCODE 14
; 15 is reserved
ISR_NOERRCODE 16
ISR_ERRCODE 17
ISR_NOERRCODE 18
ISR_NOERRCODE 19

ISR_NOERRCODE 32
ISR_NOERRCODE 33
ISR_NOERRCODE 34

; default handler:
ISR_NOERRCODE 255