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1 import logging
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211
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2 import ir
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249
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3 from target import Label, Comment, Alignment, LabelRef, Imm32, DebugInfo
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218
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4 import cortexm3 as arm
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211
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5 from ppci import CompilerError
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269
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6 import graph
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7 import flowgraph
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8 import registerallocator
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9 from instructionselector import InstructionSelector
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262
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10
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11
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268
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12 class ArmInstructionSelector(InstructionSelector):
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13 """ Instruction selector for the arm architecture """
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14 def munchExpr(self, e):
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15 if isinstance(e, ir.Alloc):
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16 return 0
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17 elif isinstance(e, ir.Binop) and e.operation == '+':
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18 a = self.munchExpr(e.value1)
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19 b = self.munchExpr(e.value2)
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20 d = self.newTmp()
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21 self.emit('add %d0, %s0, %s1', dst=[d], src=[a, b])
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22 return d
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23 elif isinstance(e, ir.Binop) and e.operation == '-':
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24 a = self.munchExpr(e.value1)
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25 b = self.munchExpr(e.value2)
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26 d = self.newTmp()
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27 self.emit('sub %d0, %s0, %s1', dst=[d], src=[a, b])
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28 return d
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29 elif isinstance(e, ir.Binop) and e.operation == '|':
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30 a = self.munchExpr(e.value1)
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31 b = self.munchExpr(e.value2)
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32 d = self.newTmp()
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33 self.emit('or %d0, %s0, %s1', dst=[d], src=[a, b])
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34 return d
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35 elif isinstance(e, ir.Binop) and e.operation == '<<':
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36 a = self.munchExpr(e.value1)
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37 b = self.munchExpr(e.value2)
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38 d = self.newTmp()
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39 self.emit('lsl %d0, %s0, %s1', dst=[d], src=[a, b])
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40 return d
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41 elif isinstance(e, ir.Binop) and e.operation == '*':
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42 a = self.munchExpr(e.value1)
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43 b = self.munchExpr(e.value2)
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44 d = self.newTmp()
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45 self.emit('mul %d0, %s0, %s1', dst=[d], src=[a, b])
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46 return d
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47 elif isinstance(e, ir.Const):
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48 d = self.newTmp()
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49 if e.value < 256:
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50 self.emit('ldr %d0, {}'.format(e.value), dst=[d])
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51 else:
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52 self.emit('ldrpcrel TODO', dst=[d])
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53 return d
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54 elif isinstance(e, ir.Mem):
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55 # Load from memory
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56 loc = self.munchExpr(e.e)
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57 d = self.newTmp()
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58 self.emit('ldr %d0, [%s0]', src=[loc], dst=[d])
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59 return d
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60 elif isinstance(e, ir.Temp):
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61 return self.getTempReg(e)
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62 else:
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63 raise NotImplementedError('--> {}'.format(e))
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64
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65 def munchStm(self, s):
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66 if isinstance(s, ir.Move) and isinstance(s.dst, ir.Mem):
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67 memloc = self.munchExpr(s.dst.e)
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68 val = self.munchExpr(s.src)
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69 self.emit('str [%s0], %s1')
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70 elif isinstance(s, ir.Move) and isinstance(s.dst, ir.Temp):
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71 val = self.munchExpr(s.src)
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72 dreg = self.getTempReg(s.dst)
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73 self.emit('mov %d0, %s0', dst=[dreg], src=[val])
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268
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74 elif isinstance(s, ir.Return):
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75 #etgt = self.targets[
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76 self.emit('jmp exit', jumps=[])
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77 elif isinstance(s, ir.Jump):
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78 tgt = self.targets[s.target]
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79 self.emit('jmp {}'.format(s), jumps=[tgt])
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268
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80 elif isinstance(s, ir.CJump):
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81 a = self.munchExpr(s.a)
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82 b = self.munchExpr(s.b)
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83 self.emit('cmp %s0, %s1', src=[a, b])
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84 ntgt = self.targets[s.lab_no]
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85 ytgt = self.targets[s.lab_yes]
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86 jmp_ins = self.makeIns('jmp {}'.format(s.lab_no), jumps=[ntgt])
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87 # Explicitely add fallthrough:
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88 self.emit('jeq {}'.format(s.lab_yes), jumps=[ytgt, jmp_ins])
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89 self.emit2(jmp_ins)
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268
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90 else:
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91 raise NotImplementedError('--> {}'.format(s))
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92
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93
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211
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94 class ArmCodeGenerator:
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95 def __init__(self, outs):
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269
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96 # TODO: schedule traces in better order.
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97 # This is optional!
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98 self.ins_sel = ArmInstructionSelector()
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99 self.outs = outs
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100 self.outs.getSection('code').address = 0x08000000
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101 self.outs.getSection('data').address = 0x20000000
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102
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103 def generate(self, ircode, cfg_file=None, ig_file=None):
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104 x = self.ins_sel.munchProgram(ircode)
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105 cfg = flowgraph.FlowGraph(x)
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106 if cfg_file:
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107 cfg.to_dot(cfg_file)
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108 ig = registerallocator.InterferenceGraph(cfg)
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109 if ig_file:
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110 ig.to_dot(ig_file)
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111
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112 regs = ['r0', 'r1', 'r2', 'r3', 'r4', 'r5', 'r6', 'r7']
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113 ra = registerallocator.RegisterAllocator()
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114 ra.registerAllocate(ig, regs)
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268
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115
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