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1 #!/usr/bin/python
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2
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199
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3 import unittest, cProfile
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200
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4 from ppci import CompilerError
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201
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5 from asmnodes import AInstruction, ABinop, AUnop, ASymbol, ALabel, ANumber
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6 from asm import tokenize, Assembler
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199
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7 import msp430
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218
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8 import cortexm3 as arm
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236
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9 import outstream
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10 from target import Label
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191
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11
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198
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12 class AssemblerLexingCase(unittest.TestCase):
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13 """ Tests the assemblers lexer """
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191
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14
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15 def testLex0(self):
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16 """ Check if the lexer is OK """
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17 asmline, toks = 'mov rax, rbx ', ['ID', 'ID', ',', 'ID']
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198
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18 self.assertSequenceEqual([tok.typ for tok in tokenize(asmline)], toks)
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191
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19
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20 def testLex1(self):
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193
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21 """ Test if lexer correctly maps some tokens """
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191
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22 asmline, toks = 'lab1: mov rax, rbx ', ['ID', ':', 'ID', 'ID', ',', 'ID']
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23 self.assertSequenceEqual([tok.typ for tok in tokenize(asmline)], toks)
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24
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193
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25 def testLex1(self):
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26 """ Test if lexer correctly maps some tokens """
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27 asmline, toks = 'mov 3.13 0xC 13', ['ID', 'REAL', 'NUMBER', 'NUMBER']
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28 self.assertSequenceEqual([tok.typ for tok in tokenize(asmline)], toks)
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29
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30 def testLex2(self):
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193
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31 """ Test if lexer fails on a token that is invalid """
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32 asmline = '0z4: mov rax, rbx $ '
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200
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33 with self.assertRaises(CompilerError):
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198
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34 list(tokenize(asmline))
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35
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36 class AssemblerParsingTestCase(unittest.TestCase):
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37 """
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38 Tests the assembler parts
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39 """
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199
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40 def setUp(self):
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41 self.a = Assembler()
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42
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43 def testParse(self):
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44 asmline = 'lab1: mov rax, rbx'
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45 self.a.parse_line(asmline)
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46
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47 def expectTree(self, asmline, stack):
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48 self.a.parse_line(asmline)
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49 self.assertSequenceEqual(stack, self.a.stack)
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50
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193
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51 def testParse2(self):
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52 asmline = 'a: mov rax, [rbx + 2]'
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195
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53 output = []
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54 output.append(ALabel('a'))
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55 output.append(AInstruction('mov', [ASymbol('rax'), AUnop('[]', ASymbol('rbx') + ANumber(2))]))
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56 self.expectTree(asmline, output)
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57
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58 def testParse3(self):
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59 # A label must be optional:
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60 asmline = 'mov rax, 1'
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61 output = [AInstruction('mov', [ASymbol('rax'), ANumber(1)])]
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62 self.expectTree(asmline, output)
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63
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64 def testParse4(self):
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65 # Test 3 operands:
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66 asmline = 'add rax, [4*rbx + 22], rcx'
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67 ops = []
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68 ops.append(ASymbol('rax'))
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69 ops.append(AUnop('[]', ANumber(4) * ASymbol('rbx') + ANumber(22)))
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70 ops.append(ASymbol('rcx'))
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71 output = [AInstruction('add', ops)]
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72 self.expectTree(asmline, output)
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73
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74 def testParse5(self):
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75 # An instruction must be optional:
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76 asmline = 'lab1:'
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77 output = []
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78 output.append(ALabel('lab1'))
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79 self.expectTree(asmline, output)
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80
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81 def testParse6(self):
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82 # A line can be empty
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83 self.a.parse_line('')
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84
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85 class AssemblerOtherTestCase(unittest.TestCase):
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86 def testWithoutTarget(self):
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87 a = Assembler()
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88 with self.assertRaises(CompilerError):
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89 a.assemble_line('')
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90
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91 @unittest.skip
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92 def testX86(self):
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93 testsrc = """ ; tst
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94 begin:
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95 mov rax, rbx ; 0x48, 0x89, 0xd8
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96 xor rcx, rbx ; 0x48, 0x31, 0xd9
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97 inc rcx ; 0x48 0xff 0xc1
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98 """
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99 a = Assembler()
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100 a.assemble(testsrc)
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101 # Compare with nasm output:
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102 nasmbytes = [0x48, 0x89, 0xd8, 0x48, 0x31, 0xd9, 0x48, 0xff, 0xc1]
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103
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104
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105 class OustreamTestCase(unittest.TestCase):
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106 def test1(self):
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107 o = outstream.BinOutputStream()
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108 o.selectSection('.text')
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109 o.emit(Label('a'))
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110 self.assertSequenceEqual(bytes(), o.Data)
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111
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112
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113 class AsmTestCaseBase(unittest.TestCase):
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114 def feed(self, line):
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115 self.a.assemble(line)
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116
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117 def check(self, hexstr):
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118 self.assertSequenceEqual(bytes.fromhex(hexstr), self.o.Data)
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119
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120
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121 class AssemblerMSP430TestCase(AsmTestCaseBase):
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122 def setUp(self):
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123 self.t = msp430.msp430target
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124 self.o = outstream.BinOutputStream()
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125 self.o.selectSection('.text')
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126 self.a = Assembler(target=self.t, stream=self.o)
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127
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128 def testMapMovInstruction(self):
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129 i = AInstruction('mov', [ASymbol('r14'), ASymbol('r15')])
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130 ri = self.t.mapInstruction(i)
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131
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132 def testMapRetiInstruction(self):
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133 i = AInstruction('reti', [])
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134 ri = self.t.mapInstruction(i)
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135
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136 @unittest.skip
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137 def testMapOperand(self):
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138 o = ASymbol('r14')
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139 mo = self.t.mapOperand(o)
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140 self.assertEqual(mo, msp430.r14)
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141
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142 @unittest.skip
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143 def testMapOperandIndirection(self):
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144 o = AUnop('[]', ASymbol('r14'))
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145 mo = self.t.mapOperand(o)
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146
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147 def testMov(self):
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148 line1 = "mov r14, r15"
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149 self.feed(line1)
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150 self.check('0F4E')
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151
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152 def testMov1337(self):
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153 line1 = "mov 0x1337, r12"
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154 self.feed(line1)
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155 self.check('3C403713')
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156
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157 def testAdd(self):
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158 line1 = "add r15, r13"
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159 self.feed(line1)
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160 self.check('0D5F')
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161
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162 def testReti(self):
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163 line1 = "reti"
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164 self.feed(line1)
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165 self.check('0013')
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166
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167 def testMSPinstructionCount(self):
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168 """ Check that there are 27 instructions """
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169 self.assertEqual(27, len(self.t.instructions))
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170
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171
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172 class AssemblerARMTestCase(AsmTestCaseBase):
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173 def setUp(self):
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174 self.t = arm.armtarget
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175 self.o = outstream.BinOutputStream()
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176 self.o.selectSection('.text')
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177 self.a = Assembler(target=self.t, stream=self.o)
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178
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179 def testMapOperand(self):
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180 pass
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181
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182 def testMovImm8(self):
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183 self.feed('mov r4, 100')
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184 self.check('6424')
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185
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186 def testYield(self):
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206
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187 self.feed('yield')
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188 self.check('10bf')
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189
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190 def testPush(self):
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191 self.feed('push {r2,r3,lr}')
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192 self.check('0cb5')
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193
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194 def testPop(self):
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195 self.feed('pop {r4-r6, pc}')
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196 self.check('70bd')
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202
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197
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212
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198 def testStr5(self):
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199 self.feed('str r4, [r1 + 0]')
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200 self.check('0c60')
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201
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202 def testLdr5(self):
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203 self.feed('ldr r4, [r0 + 0]')
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204 self.check('0468')
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205
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219
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206 def testLdrSpRel(self):
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207 self.feed('ldr r0, [sp + 4]')
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208 self.check('0198')
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209
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210 def testStrSpRel(self):
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211 self.feed('str r0, [sp + 4]')
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212 self.check('0190')
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213
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234
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214 def testLdrPcRel(self):
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215 self.feed('ldr r7, henkie')
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216 self.feed('ldr r6, henkie')
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217 self.feed('ldr r1, henkie')
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218 self.feed('align 4')
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219 self.feed('dcd 1')
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220 self.feed('henkie: dcd 2')
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221 self.check('024F024E 01490000 01000000 02000000')
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222
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223 def testBranch(self):
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224 self.feed('start: b henkie')
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225 self.feed('beq henkie')
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226 self.feed('bne henkie')
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227 self.feed('henkie: b start')
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228 self.feed('eof: b eof')
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229 self.check('01e000d0 ffd1fbe7 fee7')
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230
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231 def testBoff(self):
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232 self.feed('b henkie')
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233 self.feed('b henkie')
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234 self.feed('b henkie')
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235 self.feed('b henkie')
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236 self.feed('b henkie')
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237 self.feed('b henkie')
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238 self.feed('b henkie')
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239 self.feed('henkie:')
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240 self.feed('b henkie')
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241 self.feed('b henkie')
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242 self.feed('b henkie')
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243 self.feed('b henkie')
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244 self.check('05e004e0 03e002e0 01e000e0 ffe7fee7 fde7fce7 fbe7')
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234
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245
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218
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246 def testCmpRegReg(self):
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247 self.feed('cmp r0, r1')
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248 self.check('8842')
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249
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232
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250 def testLeftShit(self):
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251 self.feed('lsl r3, r5')
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252 self.check('ab40')
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253
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203
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254 def testSequence1(self):
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255 self.feed('mov r5, 3')
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256 self.feed('add r4, r5, 0')
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257 self.feed('loop: add r6, r4, 7')
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258 self.feed('cmp r6, 5')
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207
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259 self.check('0325 2c1c e61d 052e')
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238
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260 def testSequence2(self):
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261 self.feed('henkie:')
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262 self.feed('push {r1,r4,r5}')
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263 self.feed('add r5, r2, r4')
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264 self.feed('cmp r4, r2')
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265 self.feed('ldr r0, [sp + 4]')
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266 self.feed('str r3, [sp + 16]')
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267 self.feed('pop {r1, r4, r5}')
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268 self.feed('lsl r3, r4')
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269 self.feed('cmp r3, r5')
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270 self.feed('beq henkie')
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271 self.feed('bne henkie')
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272 self.feed('b henkie')
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273 self.check('32b41519 94420198 049332bc a340ab42 f6d0f5d1 f4e7')
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274
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275 if __name__ == '__main__':
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203
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276 #cProfile.run('unittest.main()')
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191
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277 unittest.main()
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278
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