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346
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1
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354
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2 from ppci.target.arm.instructions import Add1, Sub1, Mul1
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3 from ppci.target.arm.instructions import Ldr1, Ldr3, Adr
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346
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4
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5 %%
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6
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354
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7 %terminal ADDI32 SUBI32 MULI32 ADR
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346
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8 %terminal ORI32 SHLI32
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354
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9 %terminal CONSTI32 CONSTDATA MEMI32 REGI32 CALL
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346
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10 %terminal MOVI32
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11
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12 %%
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13
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14 reg: ADDI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Add1, dst=[d], src=[$1, $2]); return d .)
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15 reg: SUBI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Sub1, dst=[d], src=[$1, $2]); return d .)
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354
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16 reg: MULI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Mul1, dst=[d], src=[$1, $2]); return d .)
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17
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346
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18 reg: MEMI32(ADDI32(reg, cn)) 2 (. d = self.newTmp(); self.emit(Ldr1, dst=[d], src=[$1], others=[$2]); return d .)
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352
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19 reg: MEMI32(reg) 2 (. d = self.newTmp(); self.emit(Ldr1, dst=[d], src=[$1], others=[0]); return d .)
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346
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20
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21
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22 cn: CONSTI32 0 (. return $$.value .)
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23
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353
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24 reg: CONSTI32 3 (. d = self.newTmp(); ln = self.selector.frame.add_constant($$.value); self.emit(Ldr3, dst=[d], others=[ln]); return d .)
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354
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25
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26 reg: ADR(CONSTDATA) 2 (. d = self.newTmp(); ln = self.selector.frame.add_constant($$.children[0].value); self.emit(Adr, dst=[d], others=[ln]); return d .)
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27
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346
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28 reg: REGI32 1 (. return $$.value .)
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352
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29
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30 reg: CALL 1 (. return self.selector.munchCall($$.value) .)
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