from ppci.target.arm.instructions import Add1, Sub1, Mul1
from ppci.target.arm.instructions import Ldr1, Ldr3, Adr
from ppci.target.arm.instructions import And1, Lsr1, Lsl1

%%

%terminal ADDI32 SUBI32 MULI32 ADR
%terminal ORI32 SHLI32 SHRI32 ANDI32
%terminal CONSTI32 CONSTDATA MEMI32 REGI32 CALL
%terminal MOVI32

%%

reg: ADDI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Add1, dst=[d], src=[$1, $2]); return d .)
reg: SUBI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Sub1, dst=[d], src=[$1, $2]); return d .)
reg: MULI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Mul1, dst=[d], src=[$1, $2]); return d .)
reg: ANDI32(reg, reg) 2 (. d = self.newTmp(); self.emit(And1, dst=[d], src=[$1, $2]); return d .)
reg: SHRI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Lsr1, dst=[d], src=[$1, $2]); return d .)

reg: MEMI32(ADDI32(reg, cn)) 2 (. d = self.newTmp(); self.emit(Ldr1, dst=[d], src=[$1], others=[$2]); return d .)
reg: MEMI32(reg) 2 (. d = self.newTmp(); self.emit(Ldr1, dst=[d], src=[$1], others=[0]); return d .)


cn: CONSTI32 0 (. return $$.value .)

reg: CONSTI32         3 (. d = self.newTmp(); ln = self.selector.frame.add_constant($$.value); self.emit(Ldr3, dst=[d], others=[ln]); return d .)

reg: ADR(CONSTDATA)   2  (. d = self.newTmp(); ln = self.selector.frame.add_constant($$.children[0].value); self.emit(Adr, dst=[d], others=[ln]); return d .)

reg: REGI32           1 (. return $$.value .)

reg: CALL             1 (. return self.selector.munchCall($$.value) .)