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157
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1 import ppci
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158
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2 import ir
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173
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3 import registerallocator
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158
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4
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177
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5 # Instruction selection with DAG (Directed Acyclic Graph)
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6 class DagLeaf:
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7 def __init__(self, v):
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8 self.v = v
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9
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10 class DagNode:
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11 def __init__(self, name):
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12 self.name = name
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13 self.children = []
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14 def __repr__(self):
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15 return str(self.name)
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16
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17 class Dag:
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18 def __init__(self, bb):
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19 self.mapping = {}
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20 self.buildFromBB(bb)
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21 def buildFromBB(self, bb):
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22 for ins in bb.Instructions:
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23 if type(ins) is ir.BinaryOperator:
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24 if not ins.value1 in self.mapping:
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25 self.mapping[ins.value1] = DagNode(ins.value1)
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26 if not ins.value2 in self.mapping:
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27 self.mapping[ins.value2] = DagNode(ins.value2)
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28 # look for op with left and right operand the same:
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29 N = None
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30 lnode = self.mapping[ins.value1]
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31 rnode = self.mapping[ins.value2]
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32 for node in self.mapping.values():
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33 if node.name == ins.operation:
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34 if node.children[0] == lnode and node.children[1] == rnode:
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35 N = node
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36 break
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37 if not N:
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38 # Create a node.
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39 N = DagNode(ins.operation)
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40 N.children.append(lnode)
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41 N.children.append(rnode)
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42 self.mapping[ins.result] = N
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43 else:
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44 pass
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45 def dumpgv(self, outf):
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46 outf.write('subgraph {0} {{\n'.format(id(self)))
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47 for node in self.mapping.values():
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48 outf.write('{0} [label="{1}"];\n'.format(id(node), node.name))
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49 for c in node.children:
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50 outf.write('{0} -> {1};\n'.format(id(node), id(c)))
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51 outf.write('label="dag"}\n')
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52
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53 def insSelect(mod):
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54 """ Create DAG from ir-code """
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55 for bb in mod.BasicBlocks:
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56 print(bb)
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57 dag = Dag(bb)
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58 print(dag.mapping)
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59 bb.dag = dag
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60
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61 # x86 specific:
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158
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62 class AsmLabel:
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63 def __init__(self, lab):
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64 self.lab = lab
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65 def __repr__(self):
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66 return '{0}:'.format(self.lab)
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67
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68 class Op:
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171
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69 def __init__(self, op, dst, src):
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158
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70 self.op = op
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171
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71 self.src = src
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72 self.dst = dst
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158
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73 def __repr__(self):
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171
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74 return '{0} {1}, {2}'.format(self.op, self.dst, self.src)
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75
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76 class Jmp:
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77 def __init__(self, j, target):
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78 self.j = j
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79 self.target = target
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80 def __repr__(self):
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81 return '{0} {1}'.format(self.j, self.target)
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157
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82
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83 class X86CodeGen:
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84 def __init__(self, diag):
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85 self.diag = diag
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160
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86 self.regs = ['rax', 'rbx', 'rcx', 'rdx']
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157
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87
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158
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88 def emit(self, i):
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89 self.asm.append(i)
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90
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171
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91 def genBin(self, ir):
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158
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92 self.asm = []
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171
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93 # Allocate registers:
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177
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94 insSelect(ir)
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173
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95 ra = registerallocator.RegisterAllocator()
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174
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96 # TODO: do not register allocate on intermediate code:
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173
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97 ra.registerAllocate(ir, self.regs)
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171
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98 self.genModule(ir)
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99 return self.asm
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157
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100
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171
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101 def genModule(self, ir):
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174
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102 for f in ir.Functions:
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103 self.genFunction(f)
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158
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104 def genFunction(self, f):
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105 self.emit('global {0}'.format(f.name))
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106 self.emit(AsmLabel(f.name))
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174
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107 self.emit(Jmp('jmp', f.entry.name))
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158
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108 for bb in f.BasicBlocks:
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109 self.genBB(bb)
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110 def genBB(self, bb):
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171
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111 self.emit(AsmLabel(bb.name))
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158
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112 for i in bb.Instructions:
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113 self.genIns(i)
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114 def genIns(self, i):
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115 if type(i) is ir.BinaryOperator:
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171
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116 ops = {'+':'add', '-':'sub', '*':'mul'}
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117 if i.operation in ops:
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118 self.emit(Op('mov', i.result.reg, i.value1.reg))
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119 self.emit(Op(ops[i.operation], i.result.reg, i.value2.reg))
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120 else:
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121 raise NotImplementedError('op {0}'.format(i.operation))
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122 elif type(i) is ir.Load:
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174
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123 self.emit(Op('mov', i.value, '[{0}]'.format(i.location)))
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171
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124 elif type(i) is ir.Return:
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158
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125 self.emit('ret')
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171
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126 elif type(i) is ir.Call:
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160
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127 self.emit('call')
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171
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128 elif type(i) is ir.ImmLoad:
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129 self.emit(Op('mov', i.target, i.value))
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130 elif type(i) is ir.Store:
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174
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131 self.emit(Op('mov', '[{0}]'.format(i.location), i.value))
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171
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132 elif type(i) is ir.ConditionalBranch:
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133 self.emit(Op('cmp', i.a, i.b))
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134 jmps = {'>':'jg', '<':'jl', '==':'je'}
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135 if i.cond in jmps:
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136 j = jmps[i.cond]
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137 self.emit(Jmp(j, i.lab1.name))
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138 else:
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139 raise NotImplementedError('condition {0}'.format(i.cond))
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140 self.emit(Jmp('jmp', i.lab2.name))
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141 elif type(i) is ir.Branch:
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142 self.emit(Jmp('jmp', i.target.name))
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174
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143 elif type(i) is ir.Alloc:
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144 pass
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158
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145 else:
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171
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146 raise NotImplementedError('{0}'.format(i))
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158
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147
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