--- a/python/x86.py	Fri Apr 19 12:42:21 2013 +0200
+++ b/python/x86.py	Fri Apr 19 19:22:52 2013 +0200
@@ -35,18 +35,18 @@
       self.asm = []
       # Allocate registers:
       ra = registerallocator.RegisterAllocator()
+      # TODO: do not register allocate on intermediate code:
       ra.registerAllocate(ir, self.regs)
       self.genModule(ir)
       return self.asm
 
    def genModule(self, ir):
-      #for f in ir.Functions:
-      #   self.genFunction(f)
-      for bb in ir.BasicBlocks:
-         self.genBB(bb)
+      for f in ir.Functions:
+         self.genFunction(f)
    def genFunction(self, f):
       self.emit('global {0}'.format(f.name))
       self.emit(AsmLabel(f.name))
+      self.emit(Jmp('jmp', f.entry.name))
       for bb in f.BasicBlocks:
          self.genBB(bb)
    def genBB(self, bb):
@@ -62,7 +62,7 @@
          else:
             raise NotImplementedError('op {0}'.format(i.operation))
       elif type(i) is ir.Load:
-         self.emit(Op('mov', i.value, '[{0}]'.format(i.name)))
+         self.emit(Op('mov', i.value, '[{0}]'.format(i.location)))
       elif type(i) is ir.Return:
          self.emit('ret')
       elif type(i) is ir.Call:
@@ -70,7 +70,7 @@
       elif type(i) is ir.ImmLoad:
          self.emit(Op('mov', i.target, i.value))
       elif type(i) is ir.Store:
-         self.emit(Op('mov', '[{0}]'.format(i.name), i.value))
+         self.emit(Op('mov', '[{0}]'.format(i.location), i.value))
       elif type(i) is ir.ConditionalBranch:
          self.emit(Op('cmp', i.a, i.b))
          jmps = {'>':'jg', '<':'jl', '==':'je'}
@@ -82,6 +82,8 @@
          self.emit(Jmp('jmp', i.lab2.name))
       elif type(i) is ir.Branch:
          self.emit(Jmp('jmp', i.target.name))
+      elif type(i) is ir.Alloc:
+         pass
       else:
          raise NotImplementedError('{0}'.format(i))