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annotate tests/bypasstest.py @ 13:1ea479d26fce tip

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Make sure shifting phase and add bypass.py. - shifting phase is started after entering SHIFT state Transition from CAP to SHIFT does not induce shifting. - shifting phase is stoped after leaving SHIFT state. Transition from SHIFT to EXIT1 also induce a bit of shifting.
author Thinker K.F. Li <thinker@branda.to>
date Wed, 25 Feb 2009 20:08:29 +0800
parents
children
rev   line source
13
1ea479d26fce Make sure shifting phase and add bypass.py.
Thinker K.F. Li <thinker@branda.to>
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1 import sys
1ea479d26fce Make sure shifting phase and add bypass.py.
Thinker K.F. Li <thinker@branda.to>
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2 import os
1ea479d26fce Make sure shifting phase and add bypass.py.
Thinker K.F. Li <thinker@branda.to>
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3 import fcntl
1ea479d26fce Make sure shifting phase and add bypass.py.
Thinker K.F. Li <thinker@branda.to>
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4 import jtagdev
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Thinker K.F. Li <thinker@branda.to>
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5
1ea479d26fce Make sure shifting phase and add bypass.py.
Thinker K.F. Li <thinker@branda.to>
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6 if len(sys.argv) != 2:
1ea479d26fce Make sure shifting phase and add bypass.py.
Thinker K.F. Li <thinker@branda.to>
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7 print >>sys.stderr, 'Usage: %s <UART Port>' % (sys.argv[0])
1ea479d26fce Make sure shifting phase and add bypass.py.
Thinker K.F. Li <thinker@branda.to>
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8 sys.exit(1)
1ea479d26fce Make sure shifting phase and add bypass.py.
Thinker K.F. Li <thinker@branda.to>
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9 uart_fname = sys.argv[1]
1ea479d26fce Make sure shifting phase and add bypass.py.
Thinker K.F. Li <thinker@branda.to>
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10
1ea479d26fce Make sure shifting phase and add bypass.py.
Thinker K.F. Li <thinker@branda.to>
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11 try:
1ea479d26fce Make sure shifting phase and add bypass.py.
Thinker K.F. Li <thinker@branda.to>
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12 uart_fo = file(uart_fname, 'r+b')
1ea479d26fce Make sure shifting phase and add bypass.py.
Thinker K.F. Li <thinker@branda.to>
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13 except IOError, e:
1ea479d26fce Make sure shifting phase and add bypass.py.
Thinker K.F. Li <thinker@branda.to>
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14 print e
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Thinker K.F. Li <thinker@branda.to>
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15 sys.exit(1)
1ea479d26fce Make sure shifting phase and add bypass.py.
Thinker K.F. Li <thinker@branda.to>
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16 pass
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17
1ea479d26fce Make sure shifting phase and add bypass.py.
Thinker K.F. Li <thinker@branda.to>
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18 flags = fcntl.fcntl(uart_fo, fcntl.F_GETFL)
1ea479d26fce Make sure shifting phase and add bypass.py.
Thinker K.F. Li <thinker@branda.to>
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19 fcntl.fcntl(uart_fo, fcntl.F_SETFL, os.O_NONBLOCK | flags)
1ea479d26fce Make sure shifting phase and add bypass.py.
Thinker K.F. Li <thinker@branda.to>
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20
1ea479d26fce Make sure shifting phase and add bypass.py.
Thinker K.F. Li <thinker@branda.to>
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21 jtagdev.debug_frame = 1
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Thinker K.F. Li <thinker@branda.to>
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22
1ea479d26fce Make sure shifting phase and add bypass.py.
Thinker K.F. Li <thinker@branda.to>
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23 dev = jtagdev.jtagdev(uart_fo)
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24
1ea479d26fce Make sure shifting phase and add bypass.py.
Thinker K.F. Li <thinker@branda.to>
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25 dev.reset()
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Thinker K.F. Li <thinker@branda.to>
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26 dev.wait_reply()
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27
1ea479d26fce Make sure shifting phase and add bypass.py.
Thinker K.F. Li <thinker@branda.to>
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28 dev.idle();
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Thinker K.F. Li <thinker@branda.to>
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29 dev.wait_reply()
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Thinker K.F. Li <thinker@branda.to>
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30
1ea479d26fce Make sure shifting phase and add bypass.py.
Thinker K.F. Li <thinker@branda.to>
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31 dev.go_shift_IR()
1ea479d26fce Make sure shifting phase and add bypass.py.
Thinker K.F. Li <thinker@branda.to>
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32 dev.wait_reply()
1ea479d26fce Make sure shifting phase and add bypass.py.
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33
1ea479d26fce Make sure shifting phase and add bypass.py.
Thinker K.F. Li <thinker@branda.to>
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34 dev.shift_IR_n_out('\x0f', 4)
1ea479d26fce Make sure shifting phase and add bypass.py.
Thinker K.F. Li <thinker@branda.to>
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35 dev.wait_reply()
1ea479d26fce Make sure shifting phase and add bypass.py.
Thinker K.F. Li <thinker@branda.to>
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36
1ea479d26fce Make sure shifting phase and add bypass.py.
Thinker K.F. Li <thinker@branda.to>
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37 dev.go_shift_DR()
1ea479d26fce Make sure shifting phase and add bypass.py.
Thinker K.F. Li <thinker@branda.to>
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38 dev.wait_reply()
1ea479d26fce Make sure shifting phase and add bypass.py.
Thinker K.F. Li <thinker@branda.to>
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39
1ea479d26fce Make sure shifting phase and add bypass.py.
Thinker K.F. Li <thinker@branda.to>
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40 dev.shift_DR_n_out('\x01' * 128, 1024)
1ea479d26fce Make sure shifting phase and add bypass.py.
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41 dev.wait_reply()
1ea479d26fce Make sure shifting phase and add bypass.py.
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42
1ea479d26fce Make sure shifting phase and add bypass.py.
Thinker K.F. Li <thinker@branda.to>
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43 dev.go_shift_DR()
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Thinker K.F. Li <thinker@branda.to>
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44 dev.wait_reply()
1ea479d26fce Make sure shifting phase and add bypass.py.
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45
1ea479d26fce Make sure shifting phase and add bypass.py.
Thinker K.F. Li <thinker@branda.to>
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46 dev.shift_DR_n_out('\xff\xff', 16)
1ea479d26fce Make sure shifting phase and add bypass.py.
Thinker K.F. Li <thinker@branda.to>
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47 dev.wait_reply()