diff tests/bypasstest.py @ 13:1ea479d26fce tip

Make sure shifting phase and add bypass.py. - shifting phase is started after entering SHIFT state Transition from CAP to SHIFT does not induce shifting. - shifting phase is stoped after leaving SHIFT state. Transition from SHIFT to EXIT1 also induce a bit of shifting.
author Thinker K.F. Li <thinker@branda.to>
date Wed, 25 Feb 2009 20:08:29 +0800
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--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/tests/bypasstest.py	Wed Feb 25 20:08:29 2009 +0800
@@ -0,0 +1,47 @@
+import sys
+import os
+import fcntl
+import jtagdev
+
+if len(sys.argv) != 2:
+    print >>sys.stderr, 'Usage: %s <UART Port>' % (sys.argv[0])
+    sys.exit(1)
+uart_fname = sys.argv[1]
+
+try:
+    uart_fo = file(uart_fname, 'r+b')
+except IOError, e:
+    print e
+    sys.exit(1)
+    pass
+
+flags = fcntl.fcntl(uart_fo, fcntl.F_GETFL)
+fcntl.fcntl(uart_fo, fcntl.F_SETFL, os.O_NONBLOCK | flags)
+
+jtagdev.debug_frame = 1
+
+dev = jtagdev.jtagdev(uart_fo)
+
+dev.reset()
+dev.wait_reply()
+
+dev.idle();
+dev.wait_reply()
+
+dev.go_shift_IR()
+dev.wait_reply()
+
+dev.shift_IR_n_out('\x0f', 4)
+dev.wait_reply()
+
+dev.go_shift_DR()
+dev.wait_reply()
+
+dev.shift_DR_n_out('\x01' * 128, 1024)
+dev.wait_reply()
+
+dev.go_shift_DR()
+dev.wait_reply()
+
+dev.shift_DR_n_out('\xff\xff', 16)
+dev.wait_reply()